Invention Grant
- Patent Title: Structure and method for fully depleted silicon on insulator structure for threshold voltage modification
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Application No.: US14970725Application Date: 2015-12-16
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Publication No.: US09941300B2Publication Date: 2018-04-10
- Inventor: John Joseph Ellis-Monaghan , Terence B Hook , Kirk David Peterson
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent Yuanmin Cai
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/06 ; H01L29/66 ; H01L21/762 ; H01L27/11 ; H01L21/84 ; H01L21/66 ; H01L29/10

Abstract:
A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.
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