公开(公告)号：US20170179156A1

公开(公告)日：2017-06-22

申请号：US14970725

申请日：2015-12-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： John Joseph Ellis-Monaghan ,  Terence B. Hook ,  Kirk David Peterson

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/10 ,  H01L27/11 ,  H01L21/84 ,  H01L21/66 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/84 ,  H01L22/20 ,  H01L27/11 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/4908 ,  H01L29/66568 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/78696

Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.

公开(公告)号：US09941300B2

公开(公告)日：2018-04-10

申请号：US14970725

申请日：2015-12-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： John Joseph Ellis-Monaghan ,  Terence B Hook ,  Kirk David Peterson

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L27/11 ,  H01L21/84 ,  H01L21/66 ,  H01L29/10

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/84 ,  H01L22/20 ,  H01L27/11 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/4908 ,  H01L29/66568 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/78696

Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.