Invention Grant
- Patent Title: Testing of power on reset (POR) and unmaskable voltage monitors
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Application No.: US15615178Application Date: 2017-06-06
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Publication No.: US09941875B2Publication Date: 2018-04-10
- Inventor: Venkata Narayanan Srinivasan , Srinivas Dhulipalla
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Schiphol
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Schiphol
- Agency: Gardere Wynne Sewell LLP
- Main IPC: H03K17/22
- IPC: H03K17/22 ; H03K19/20 ; H03K5/19

Abstract:
A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.
Public/Granted literature
- US20180013418A1 TESTING OF POWER ON RESET (POR) AND UNMASKABLE VOLTAGE MONITORS Public/Granted day:2018-01-11
Information query
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