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    TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES
    1.
    发明申请
    TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES 有权

    公开(公告)号：US20240426907A1

    公开(公告)日：2024-12-26

    申请号：US18338082

    申请日：2023-06-20

    Applicant: STMicroelectronics International N.V.

    Inventor： Shiv Kumar Vats ,  Umesh Chandra Srivastava ,  Venkata Narayanan Srinivasan

    IPC: G01R31/3185

    Abstract: An integrated circuit includes a first set and a second set of scan flip flops, a circuit under test, and a controller. Each scan flip flop of the first set includes a scan enable input coupled to a first scan enable signal. The circuit under test includes logic elements downstream of the first set. The second set includes at least one scan flip flop downstream of the logic elements. Each scan flip flop of the second set includes a scan enable input coupled to a second scan enable signal. The controller is configured to test the logic elements by shifting test patterns into the first set while asserting both the first and second scan enable signal, launching the test patterns, and capturing results from the second set while continuing to assert the first scan enable signal and deasserting the second scan enable signal.

    METHODS AND DEVICES FOR BYPASSING A VOLTAGE REGULATOR
    6.
    发明申请
    METHODS AND DEVICES FOR BYPASSING A VOLTAGE REGULATOR 有权

    公开(公告)号：US20220308610A1

    公开(公告)日：2022-09-29

    申请号：US17211545

    申请日：2021-03-24

    Applicant: STMicroelectronics International N.V.

    Inventor： Venkata Narayanan Srinivasan ,  Mayankkumar Hareshbhai Niranjani ,  Gourav Garg

    IPC: G05F1/56 ,  G01R31/28

    Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.

    COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE
    8.
    发明申请
    COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE 审中-公开

    公开(公告)号：US20190064270A1

    公开(公告)日：2019-02-28

    申请号：US15688184

    申请日：2017-08-28

    Applicant: STMicroelectronics International N.V.

    Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

    IPC: G01R31/3185 ,  G06F11/267 ,  G06F11/27 ,  G01R31/3183

    Abstract: A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debuging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.

    Circuit and method for scan testing
    10.
    发明授权
    Circuit and method for scan testing 有权

    公开(公告)号：US11714131B1

    公开(公告)日：2023-08-01

    申请号：US17699900

    申请日：2022-03-21

    Applicant: STMicroelectronics International N.V.

    Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Shiv Kumar Vats ,  Umesh Chandra Srivastava

    IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/318533 ,  G01R31/318552 ,  G01R31/3177 ,  G01R31/31725

    Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.

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