Invention Grant
- Patent Title: Correlated double sampling (CDS) circuit for decreasing settling time and image sensor including the same
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Application No.: US15438060Application Date: 2017-02-21
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Publication No.: US09942496B2Publication Date: 2018-04-10
- Inventor: Sang Hoon Ha , Ji Yong Park , Kwang Hyun Lee
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2016-0041829 20160405
- Main IPC: H04N5/357
- IPC: H04N5/357 ; H01L27/146 ; H04N5/363 ; H04N5/365 ; H04N5/3745 ; H04N5/378

Abstract:
A correlated double sampling (CDS) circuit includes a comparator and a first circuit. The comparator including, a first input terminal, a second input terminal, at least one output terminal, and a plurality of first transistors operably coupled between the at least one output terminal and the first and second input terminals. The first circuit includes at least one second transistor, the at least one second transistor operably coupled to the at least one output terminal and one of the first input terminal and the second input terminal, the at least one second transistor having at least one of (i) a different number of layers than the first transistors, and (ii) a different dimension than the first transistors.
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