Invention Grant
- Patent Title: Controlling persistent writes to non-volatile memory based on persist buffer data and a persist barrier within a sequence of program instructions
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Application No.: US14927725Application Date: 2015-10-30
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Publication No.: US09946492B2Publication Date: 2018-04-17
- Inventor: Stephan Diestelhorst , Aasheesh Kolli , Ali Ghassan Saidi , Peter Chen , Thomas Friedrich Wenisch
- Applicant: ARM Limited , The Regents of the University of Michigan
- Applicant Address: GB Cambridge US MI Ann Arbor
- Assignee: ARM Limited,The Regents of the University of Michigan
- Current Assignee: ARM Limited,The Regents of the University of Michigan
- Current Assignee Address: GB Cambridge US MI Ann Arbor
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F3/06 ; G11C16/10 ; G06F13/28 ; G06F12/02

Abstract:
A data processing system 2 including non-volatile memory 22 manages the ordering of writes to the non-volatile memory and persist barrier instructions using a persist buffer storing persist buffer data. A write controller responds to the persist buffer data to prevent writing to the non-volatile memory for instructions following a given persist barrier instruction within a sequence of program instructions before the writes to the non-volatile memory which precede that given persist barrier instruction have at least been acknowledged as received by the memory system containing the non-volatile memory. In the case of a multi-core system, cache snooping mechanisms are used to pass persistency dependence data between cores such that strong persist atomicity may be tracked and managed between the cores.
Public/Granted literature
- US20170123723A1 CONTROLLING MEMORY ACCESS TO NON-VOLATILE MEMORY Public/Granted day:2017-05-04
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