A cache coherence mechanism may comprise a bit-to-cache map for processor cores operable up to a maximum frequency for cores of a multicore processor. Entries in a cache coherence directory may include a bit field identifying cores operable at or near the maximum frequency that share a memory block corresponding to the entry. An additional field may indicate sharing by cores operating at lower frequencies. The additional field may be indicative of the bit-field corresponding to a bit-to-cache map representative of cores other than those operating at or near the maximum frequency.