公开(公告)号：US10346227B2

公开(公告)日：2019-07-09

申请号：US15401114

申请日：2017-01-09

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F12/00 ,  G06F11/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/50 ,  G11C11/406 ,  G11C7/10 ,  G11C11/4074 ,  G11C29/00 ,  G11C11/40

Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.

公开(公告)号：US10289452B2

公开(公告)日：2019-05-14

申请号：US15495126

申请日：2017-04-24

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F9/50 ,  G06F9/48 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0813 ,  G06F11/34

Abstract: Methods and systems to assign threads in a multi-core processor are disclosed. A method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.

公开(公告)号：US09772950B2

公开(公告)日：2017-09-26

申请号：US14437331

申请日：2012-10-25

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F12/0897 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0817

CPC classification number: G06F12/0897 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0826 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/251 ,  G06F2212/301

Abstract: Technologies are generally described for methods and systems effective to maintain coherence in a multi-core processor on a die. In an example, a method for processing a request for a particular block in a particular region may include analyzing, by a first processor, a first cache to determine whether there is a block indicator in the first cache associated with the particular block. The method may further include when the first processor determines that the block indicator is not present in the first cache, analyzing, by the first processor, the first cache to determine whether there is a region indicator associated with the particular region. The method may further include when the first processor determines that the region indicator is not present in the first cache, the method further includes sending, by the first processor, the request to the directory in the tile.

公开(公告)号：US20170116058A1

公开(公告)日：2017-04-27

申请号：US15401114

申请日：2017-01-09

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F11/00 ,  G11C11/4074 ,  G11C11/406

CPC classification number: G06F11/004 ,  G11C7/1072 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4074 ,  G11C29/023 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50016 ,  G11C29/783 ,  G11C2211/4061

Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.

公开(公告)号：US09501350B2

公开(公告)日：2016-11-22

申请号：US14492186

申请日：2014-09-22

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/34

CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/5678 ,  G11C29/42 ,  G11C29/52

Abstract: Technologies are generally described herein to detect unidirectional resistance drift errors in a multilevel cell of a phase change memory. The resistance levels of the multilevel cell of the phase change memory may be encoded to detect unidirectional resistance drift errors. In some examples, Berger Code-compatible encoding may be used. When a word is written to the multilevel cell, a write check code may be generated. The write check code may be a binary representation of the number of zeroes contained in the word as written. When the word is read from the multilevel cell, a read check code may be generated. The read check code may be a binary representation of the number of zeroes contained in the word as read. An error can be detected if a comparison indicates that the write check code and the read check code are different.

Abstract translation: 这里通常描述技术来检测相变存储器的多电平单元中的单向电阻漂移误差。 可以编码相变存储器的多电平单元的电阻电平以检测单向电阻漂移误差。 在一些示例中，可以使用Berger Code兼容的编码。 当一个单词写入多层单元时，可能会生成一个写检查代码。 写检查码可以是写入的单词中包含的零数的二进制表示。 当从多级单元读取该单词时，可以生成读取校验码。 读取校验码可以是包含在读取的单词中的零数的二进制表示。 如果比较指示写入检查码和读取校验码不同，则可以检测到错误。

公开(公告)号：US20160217080A1

公开(公告)日：2016-07-28

申请号：US14603277

申请日：2015-01-22

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0837 ,  G06F12/0879 ,  G06F2212/1044 ,  G06F2212/6042 ,  Y02D10/13

Abstract: Techniques are generally described for cache management in a processor with a cache. In response to receiving a bulk memory modification instruction, data blocks of the cache associated with the bulk memory modification instruction may be identified. A cache coherence state of the identified data blocks may also be identified. The updated cache coherence state may be indicative of a zero value of the data blocks and the cache coherence state of the identified data blocks may be updated without modification to a cache data array.

Abstract translation: 一般来说，在具有高速缓存的处理器中用于高速缓存管理的技术。 响应于接收批量存储器修改指令，可以识别与大容量存储器修改指令相关联的高速缓存的数据块。 还可以识别所标识的数据块的高速缓存相干状态。 更新的高速缓存一致状态可以指示数据块的零值，并且可以在不修改高速缓存数据阵列的情况下更新所识别的数据块的高速缓存一致状态。

公开(公告)号：US20160048447A1

公开(公告)日：2016-02-18

申请号：US14442093

申请日：2014-03-28

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0238 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/222 ,  G06F2212/604 ,  Y02D10/13

Abstract: Technologies are generally described manage MRAM cache writes in processors. In some examples, when a write request is received with data to be stored in an MRAM cache, the data may be evaluated to determine whether the data is to be further processed. In response to a determination that the data is to be further processed, the data may be stored in a write cache associated with the MRAM cache. In response to a determination that the data is not to be further processed, the data may be stored in the MRAM cache.

Abstract translation: 技术通常被描述为在处理器中管理MRAM缓存写入。 在一些示例中，当接收到要存储在MRAM高速缓存中的数据的写请求时，可以评估数据以确定数据是否被进一步处理。 响应于要进一步处理数据的确定，数据可以存储在与MRAM高速缓存相关联的写高速缓存中。 响应于确定数据不被进一步处理，数据可以存储在MRAM缓存中。

公开(公告)号：US09251072B2

公开(公告)日：2016-02-02

申请号：US14687452

申请日：2015-04-15

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0817 ,  G06F12/082 ,  G06F12/122 ,  G06F12/123 ,  G06F2212/1008 ,  G06F2212/283 ,  G06F2212/621 ,  Y02D10/13

Abstract: Technologies are generally described for a cache coherence directory in multi-processor architectures. In an example, a directory in a die may receive a request for a particular block. The directory may determine a block aging threshold relating to a likelihood that data blocks, including the particular data block, are stored in one or more caches in the die. The directory may further analyze a memory to identify a particular cache indicated as storing the particular data block and identify a number of cache misses for the particular cache. The directory may identify a time when an event occurred for the particular data block and determine whether to send the request for the particular data block to the particular cache based on the aging threshold, the time of the event, and the number of cache misses.

公开(公告)号：US09166930B2

公开(公告)日：2015-10-20

申请号：US13823361

申请日：2012-10-30

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: H04L12/937 ,  H04L12/933 ,  H04L12/773

CPC classification number: H04L49/253 ,  H04L45/60 ,  H04L49/109

Abstract: Technologies generally described herein relate to waved time multiplexing. In some examples, a command flit can be transmitted from a sender node of a network-on-chip (“NOC”) to a destination node of the NOC via an intermediate node along a circuit-switched path. The command flit can include an interval period and a release duration. When the command flit has been transmitted, one or more data flits can be transmitted from the sender node to the destination node via the intermediate node along the circuit-switched path. The sender node, the destination node, and the intermediate node can be configured to reserve router resources of the sender node, the destination node, and the intermediate node respectively for circuit-switched traffic during a use duration of the interval period and to release the router resources for packet-switched traffic during the release duration in a waved time multiplex arrangement.

Abstract translation: 这里通常描述的技术涉及波形时间复用。 在一些示例中，可以通过沿着电路交换路径的中间节点从片上网络（“NOC”）的发送者节点向NOC的目的地节点发送命令转发。 命令flit可以包括间隔时间和释放持续时间。 当发送命令时，可以沿着电路交换路径经由中间节点从发送方节点向目的地节点发送一个或多个数据流。 发送方节点，目的地节点和中间节点可以被配置为在间隔周期的使用持续时间期间分别为发送方节点，目的地节点和中间节点预留路由器资源以用于电路交换业务，并且释放 在波形时间复用布置期间的释放持续时间期间用于分组交换业务的路由器资源。

公开(公告)号：US20140366030A1

公开(公告)日：2014-12-11

申请号：US14009750

申请日：2013-06-06

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC

Inventor： Yan Solihin

IPC: G06F9/48

CPC classification number: G06F9/4856 ,  G06F12/084 ,  G06F12/0842 ,  Y02D10/13 ,  Y02D10/24 ,  Y02D10/32

Abstract: Technologies are generally described for methods, systems and processors effective to migrate a thread. The thread may be migrated from the first core to the second core. The first and the second core may be configured in communication with a first cache. The first core may generate a request for a first data block from the first cache. In response to a cache miss in the first cache for the first data block, the first core may generate a request for the first data block from a memory. The first core may coordinate with a second cache to store the first data block in the second cache. The thread may be migrated from the second core to a third core. The second core and third core may be configured in communication with the second cache.

Abstract translation: 通常描述有效迁移线程的方法，系统和处理器的技术。 线程可以从第一核心迁移到第二核心。 第一和第二核可以被配置为与第一高速缓存通信。 第一核可以从第一缓存生成对第一数据块的请求。 响应于用于第一数据块的第一高速缓存中的高速缓存未命中，第一核可以从存储器生成对第一数据块的请求。 第一核心可以与第二缓存器协调以将第一数据块存储在第二高速缓存中。 线程可以从第二核心迁移到第三核心。 第二核心和第三核心可以被配置为与第二高速缓存通信。