Invention Grant
- Patent Title: Method for manufacturing semiconductor device including memory cell of nonvolatile memory, capacitance element, and transistors
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Application No.: US15417050Application Date: 2017-01-26
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Publication No.: US09947776B2Publication Date: 2018-04-17
- Inventor: Atsushi Amo
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC.
- Priority: JP2016-056819 20160322
- Main IPC: H01L21/8242
- IPC: H01L21/8242 ; H01L29/66 ; H01L29/792 ; H01L27/11568 ; H01L27/06 ; H01L23/522 ; H01L29/40

Abstract:
To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an upper electrode is embedded in a trench formed in a main surface of a semiconductor substrate are mixed together.After an insulating film is formed over a main surface of a semiconductor substrate so as to cover a trench formed in the main surface of the semiconductor substrate, the insulating film is processed to form an upper electrode of a capacitive element, a gate insulating film which insulates the semiconductor substrate to be a lower electrode, and a gate insulting film of a high breakdown voltage transistor.
Public/Granted literature
- US20170278954A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2017-09-28
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