- 专利标题: Spread spectrum clocking phase error cancellation for analog CDR/PLL
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申请号: US15256444申请日: 2016-09-02
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公开(公告)号: US09960774B2公开(公告)日: 2018-05-01
- 发明人: Amir Amirkhany , Ashkan Roshan Zamir
- 申请人: Samsung Display Co., Ltd.
- 申请人地址: KR Yongin-si
- 专利权人: Samsung Display Co., Ltd.
- 当前专利权人: Samsung Display Co., Ltd.
- 当前专利权人地址: KR Yongin-si
- 代理机构: Lewis Roca Rothgerber Christie LLP
- 主分类号: H04B3/46
- IPC分类号: H04B3/46 ; H03L7/08 ; H03L7/099 ; H03L7/089 ; H03L7/093 ; H04L12/801
摘要:
A system and method for correcting for phase errors, in a phase locked loop, resulting from spread spectrum clocking involving a reference clock signal having a frequency modulation. A correction generation circuit generates an offset signal, that when injected after the charge pump of the phase locked loop, causes the voltage controlled oscillator to produce a signal with substantially the same frequency modulation, thereby reducing the phase error. The correction generation circuit may include a timing estimation circuit for estimating the times at which transitions (between positive-sloping and negative-sloping portions of the triangle wave) occur, and an amplitude estimation circuit for estimating the amplitude of the offset signal that results in a reduction in the phase error.
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