Invention Grant
- Patent Title: Strain release in pFET regions
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Application No.: US15343387Application Date: 2016-11-04
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Publication No.: US09966387B2Publication Date: 2018-05-08
- Inventor: Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Darsen D. Lu , Alexander Reznicek , Kern Rim
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Nicholas L. Cadmus
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/84 ; H01L21/3065 ; H01L29/161 ; H01L27/092 ; H01L29/66 ; H01L29/78 ; H01L29/10 ; H01L21/762 ; H01L29/423 ; H01L21/8238

Abstract:
A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.
Public/Granted literature
- US20170053943A1 STRAIN RELEASE IN PFET REGIONS Public/Granted day:2017-02-23
Information query
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