- 专利标题： Memory controller with data compression and padding features, method of controlling nonvolatile memory and memory system
-
申请号： US15260963申请日： 2016-09-09
-
公开(公告)号： US09971523B2公开(公告)日： 2018-05-15
- 发明人: Sho Kodama , Keiri Nakanishi , Kohei Oikawa , Kojiro Suzuki
- 申请人： Toshiba Memory Corporation
- 申请人地址： JP Tokyo
- 专利权人： Toshiba Memory Corporation
- 当前专利权人： Toshiba Memory Corporation
- 当前专利权人地址： JP Tokyo
- 代理机构： White & Case LLP
- 主分类号： G06F3/06
- IPC分类号： G06F3/06 ; G06F11/10 ; G11C29/52
摘要：
According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit compresses first data to be written into a first page and second data to be written into a second page. The padding processing unit performs a padding processing such that the compressed first data is written into first memory cells, first padding data is written into second memory cells, the compressed second data is written into third memory cells, and second padding data is written into fourth memory cells.
公开/授权文献
信息查询
