Invention Grant
- Patent Title: Layout construction for addressing electromigration
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Application No.: US13975185Application Date: 2013-08-23
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Publication No.: US09972624B2Publication Date: 2018-05-15
- Inventor: Seid Hadi Rasouli , Michael Joseph Brunolli , Christine Sung-An Hau-Riege , Mickael Malabry , Sucheta Kumar Harish , Prathiba Balasubramanian , Kamesh Medisetti , Nikolay Bomshtein , Animesh Datta , Ohsang Kwon
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox, LLP and Qualcomm, Incorporated
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H03K17/16 ; H03K17/687 ; H01L23/482 ; H01L27/02 ; H01L23/522

Abstract:
A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.
Public/Granted literature
- US20150054568A1 LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION Public/Granted day:2015-02-26
Information query
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