Invention Grant
- Patent Title: Semiconductor integrated circuit device
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Application No.: US15635970Application Date: 2017-06-28
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Publication No.: US09972629B2Publication Date: 2018-05-15
- Inventor: Koji Nii
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/11 ; H01L23/528 ; H01L29/78 ; G11C11/412

Abstract:
In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.
Public/Granted literature
- US20170301678A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2017-10-19
Information query
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