A display apparatus includes a printed circuit board (PCB). A power management integrated circuit (PMIC) is mounted on the PCB and is configured to generate first to fourth gate clock signals and first to fourth inversion gate clock signals. A phase of the first gate clock signal partially overlaps a phase of the second to fourth gate clock signal. Each of the first to fourth inversion gate clock signals has a phase opposite to that of a respective one of the first to fourth gate clock signals. A gate driver generates a plurality of gate signals based on the first to fourth gate clock signals and the first to fourth inversion gate clock signals and applies the plurality of gate signals to a plurality of gate lines. A display panel is connected to the plurality of gate lines.