- 专利标题： Integrated circuit with NMOS and PMOS transistors having different threshold voltages through channel doping and gate material work function schemes
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申请号： US15652925申请日： 2017-07-18
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公开(公告)号： US09985029B2公开(公告)日： 2018-05-29
- 发明人: Francois Andrieu
- 申请人： Commissariat a l'energie atomique et aux energies alternatives
- 申请人地址： FR Paris
- 专利权人： Commissariat à l'energie atomique et aux énergies alternatives
- 当前专利权人： Commissariat à l'energie atomique et aux énergies alternatives
- 当前专利权人地址： FR Paris
- 代理机构： Oblon, McClelland, Maier & Neustadt, L.L.P.
- 优先权： FR1657020 20160722
- 主分类号： H01L27/092
- IPC分类号： H01L27/092 ; H01L27/12 ; H01L29/78 ; H01L29/06 ; H01L29/49
摘要：
An integrated circuit comprising: first to third nMOS transistors with different threshold voltages, and first to third pMOS transistors with different threshold voltages, the nMOS transistors having channel regions made of silicon subjected to tensile stress and/or said pMOS transistors having channel regions made of SiGe subjected to compressive stress; a first well and a second well that are arranged underneath the nMOS transistors and underneath the pMOS transistors, respectively, with one and the same doping; two nMOS gate stacks comprising one and the same material, two of the nMOS gate stacks comprising materials having separate work functions, an nMOS gate stack having one and the same material as a pMOS gate stack, with the equation: Gp*Vdds−Gn*Gnds=Sn*|σn|+Sp*(|σp|−1.65*109)−VarCais+K.
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