公开(公告)号：US10418486B2

公开(公告)日：2019-09-17

申请号：US15976452

申请日：2018-05-10

申请人： STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Remy Berthelon ,  Francois Andrieu

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L27/092 ,  H01L21/762 ,  H01L29/786

摘要： Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.

公开(公告)号：US09147750B2

公开(公告)日：2015-09-29

申请号：US13902793

申请日：2013-05-25

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Simeon Morvan ,  Francois Andrieu ,  Raluca Tiron

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L21/033 ,  H01L21/308

CPC分类号： H01L29/66568 ,  H01L21/0337 ,  H01L21/3086 ,  H01L29/66545 ,  H01L29/66795

摘要： A process for fabricating one transistor, comprising a semiconductor region, comprising a source region, a drain region, and a channel region covered with a gate, comprises: production of an primary etching mask on the surface of the semiconductor region, said mask containing at least one primary aperture; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures; etching said active region through said secondary apertures in order to define nanoscale self-aligned semiconductor features; producing said gate on the surface of said self-aligned semiconductor features.

摘要翻译： 一种用于制造一个晶体管的方法，包括半导体区域，包括源极区域，漏极区域和被栅极覆盖的沟道区域，包括：在半导体区域的表面上产生初级蚀刻掩模，所述掩模包含在 至少一个主孔; 在所述主孔中沉积嵌段共聚物，其交替地含有至少第一聚合物区域和第二聚合物区域; 去除一系列第一聚合物结构域或一系列第二聚合物结构域，以便产生含有次级孔的次级掩模; 通过所述次级孔蚀刻所述有源区，以便限定纳米尺度的自对准半导体特征; 在所述自对准半导体特征的表面上产生所述栅极。

公开(公告)号：US20190312039A1

公开(公告)日：2019-10-10

申请号：US16379476

申请日：2019-04-09

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

发明人： Francois Andrieu ,  Remy Berthelon ,  Bastien Giraud

IPC分类号： H01L27/11 ,  G11C11/419

摘要： The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

公开(公告)号：US09985029B2

公开(公告)日：2018-05-29

申请号：US15652925

申请日：2017-07-18

申请人： Commissariat a l'energie atomique et aux energies alternatives

发明人： Francois Andrieu

IPC分类号： H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

CPC分类号： H01L27/0922 ,  H01L21/823828 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66886 ,  H01L29/7848 ,  H01L29/78648

摘要： An integrated circuit comprising: first to third nMOS transistors with different threshold voltages, and first to third pMOS transistors with different threshold voltages, the nMOS transistors having channel regions made of silicon subjected to tensile stress and/or said pMOS transistors having channel regions made of SiGe subjected to compressive stress; a first well and a second well that are arranged underneath the nMOS transistors and underneath the pMOS transistors, respectively, with one and the same doping; two nMOS gate stacks comprising one and the same material, two of the nMOS gate stacks comprising materials having separate work functions, an nMOS gate stack having one and the same material as a pMOS gate stack, with the equation: Gp*Vdds−Gn*Gnds=Sn*|σn|+Sp*(|σp|−1.65*109)−VarCais+K.

公开(公告)号：US08853023B2

公开(公告)日：2014-10-07

申请号：US13753436

申请日：2013-01-29

申请人： Commissariat a l'Energie Atomique et aux Energies Alternatives

发明人： Simeon Morvan ,  Francois Andrieu ,  Jean-Charles Barbe

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/762 ,  H01L21/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L21/02107 ,  H01L21/76232 ,  H01L22/12 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78684

摘要： A method for stressing a pattern having a pattern surface, in a layer of semiconductive material that can be silicon on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy SixGey with x and y being molar fractions, and a buried layer of silicon oxide, comprises: etching at the periphery of a surface of dimensions greater than said pattern surface, of the buried layer of silicon oxide and layer of alloy SixGey over a part of the depth of said layer of alloy; the buried layer of silicon oxide being situated between said layer of semiconductive material and said stress layer of alloy SixGey. In a transistor structure, etching at the periphery of said surface obtains a pattern thus defined having dimensions greater than the area of interest situated under the gate of the transistor.

摘要翻译： 一种用于在具有图案表面的图案上应力的方法，该半导体材料层可以是在衬底的表面上产生的层叠层的表面上的硅，所述堆叠包括至少一个合金SixGey与x的应力层 并且y是摩尔分数，以及氧化硅的掩埋层，包括：在尺寸大于所述图案表面的表面的周边，在氧化硅的掩埋层和合金SixGey层的一部分深度处蚀刻 所述合金层; 氧化硅的掩埋层位于所述半导体材料层和合金SixGey的所述应力层之间。 在晶体管结构中，在所述表面的周边处的蚀刻获得如此限定的图案，其尺寸大于位于晶体管栅极之下的感兴趣区域。

公开(公告)号：US11810789B2

公开(公告)日：2023-11-07

申请号：US16709993

申请日：2019-12-11

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Shay Reboh ,  Victor Boureau ,  Sylvain Maitrejean ,  Francois Andrieu

IPC分类号： H01L21/308 ,  H01L21/02 ,  H01L21/8234

CPC分类号： H01L21/3083 ,  H01L21/0245 ,  H01L21/02249 ,  H01L21/3081 ,  H01L21/8234

摘要： A method for producing a semiconductor substrate is provided, including: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the region; etching the superficial layer to a pattern of the mask, exposing a first lateral edge of a first strained semiconductor portion belonging to the part and contacting the dielectric layer; forming a mechanical barrier from a second portion of material belonging to the first portion, the second portion having a bottom surface contacting the dielectric layer and an upper surface contacting the mask, the barrier arranged against the part and bearing mechanically against the second portion, and removing the mask.

公开(公告)号：US11024544B2

公开(公告)日：2021-06-01

申请号：US16221939

申请日：2018-12-17

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Francois Andrieu ,  Lamine Benaissa ,  Laurent Brunet

IPC分类号： H01L21/00 ,  H01L21/822 ,  H01L21/768 ,  H01L27/12 ,  H01L27/06 ,  H01L21/20 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234

摘要： Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.

公开(公告)号：US10741565B2

公开(公告)日：2020-08-11

申请号：US16379476

申请日：2019-04-09

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

发明人： Francois Andrieu ,  Remy Berthelon ,  Bastien Giraud

IPC分类号： G11C11/41 ,  H01L27/11 ,  G11C11/419 ,  H01L21/822 ,  H01L27/06 ,  H01L27/12

摘要： The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

公开(公告)号：US09520330B2

公开(公告)日：2016-12-13

申请号：US14978428

申请日：2015-12-22

申请人： Commissariat a L'Energie Atomique et aux Energies Alternatives ,  International Business Machines Corporation

发明人： Francois Andrieu ,  Nicolas Degors ,  Pierre Perreau

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/1203

摘要： There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon—germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon—germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.

摘要翻译： 提供了一种用于制造集成电路的方法，该集成电路包括基板和形成在基板上的绝缘层; 第一pMOS晶体管，其形成在所述绝缘层上，并且包括形成在第一层硅 - 锗合金中的沟道，具有第一厚度和第一平均锗密度; 具有第一等效氧化物厚度的栅极氧化物层; 形成在所述绝缘层上的第二pMOS晶体管，并且还包括形成在硅 - 锗合金的第二层中的沟道，所述沟道的第二厚度大于比所述第一厚度低的所述第一和第二平均锗密度; 以及具有大于第一等效氧化物厚度的第二等效氧化物厚度的栅极氧化物层。

公开(公告)号：US11139209B2

公开(公告)日：2021-10-05

申请号：US16716659

申请日：2019-12-17

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Perrine Batude ,  Francois Andrieu

IPC分类号： H01L21/822 ,  H01L21/84 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768

摘要： A production of a device with superimposed levels of components including in this order providing on a given level N1 provided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N2, above said given level N1, the stack including a ground plane layer situated between the first and second semiconductor layers as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer. A gate is formed on at least one island. Distinct portions are etched in the second semiconductor ground plane layer. An isolation zone is formed around the island by the gate and the island.