Invention Grant
- Patent Title: Chunk redundancy architecture for memory
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Application No.: US15638042Application Date: 2017-06-29
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Publication No.: US09996438B2Publication Date: 2018-06-12
- Inventor: Toru Tanzawa
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F11/20
- IPC: G06F11/20

Abstract:
An integrated circuit (IC) includes addressable blocks of memory, and at least one redundant block of memory. A block of memory includes two or more chunks of memory. The IC also includes redundancy control cells. Control circuitry is included to access a first chunk of a redundant block of memory in place of a first remapped chunk one of the addressable blocks of memory, and a second chunk of a redundant block of memory in place of a second remapped chunk one of the addressable blocks of memory, based on the redundancy control cells.
Public/Granted literature
- US20170300395A1 CHUNK REDUNDANCY ARCHITECTURE FOR MEMORY Public/Granted day:2017-10-19
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