A bit operation processor having a first address operation unit for updating the address of data in units of a byte or multiple bytes for performing operation in units of a byte or multiple bytes. A second address operation unit for updating the address of data in units of a bit or multiple bits, an address controller operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit. Fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.