公开(公告)号：US5287523A

公开(公告)日：1994-02-15

申请号：US597464

申请日：1990-10-09

申请人： Nigel J. Allison ,  Janice L. Benzel ,  Joseph F. Kowalski

发明人： Nigel J. Allison ,  Janice L. Benzel ,  Joseph F. Kowalski

IPC分类号： G06F9/38 ,  G06F13/24 ,  G06F9/20

CPC分类号： G06F9/3861 ,  G06F13/24

摘要： A method for servicing peripheral interrupt requests in a data processing system is provided. A state vector register stores a current state of a state machine which controls the interrupt-generating peripheral. In addition, the state vector register simultaneously stores an interrupt source identifier, which indicates the source of the highest priority interrupt request currently pending for the interrupt-generating peripheral. When the processor receives an interrupt request, the value stored in the state vector register of the interrupt-generating peripheral is read into an index register in the processor. The processor then uses the value as an index into a jump table, stored in memory, which contains the interrupt service routines. The use of the state vector register in conjunction with existing internal signals enables the processor to rapidly retrieve the appropriate interrupt service routine from memory, while minimizing the system overhead associated with servicing the interrupt request.

摘要翻译： 提供了一种用于在数据处理系统中维护外围中断请求的方法。 状态向量寄存器存储控制中断产生外设的状态机的当前状态。 另外，状态向量寄存器同时存储一个中断源标识符，它指示中断产生外设当前待处理的最高优先级中断请求的源。 当处理器接收到中断请求时，存储在中断产生外设的状态向量寄存器中的值被读入处理器中的索引寄存器。 然后，处理器将该值用作索引到存储在存储器中的跳转表，其中包含中断服务程序。 结合现有内部信号使用状态向量寄存器使得处理器可以从存储器快速检索适当的中断服务程序，同时最小化与维护中断请求相关的系统开销。

公开(公告)号：US4646262A

公开(公告)日：1987-02-24

申请号：US821742

申请日：1986-01-23

申请人： David M. Smith

发明人： David M. Smith

IPC分类号： G09G5/393 ,  G06F9/20

CPC分类号： G09G5/393

摘要： A method and apparatus for writing a vector of data into a random access memory at high speed wherein the random access memory (RAM) is partitioned into blocks of addressable storage sites and wherein storage sites within each block are individually accessible. A vector generator provides addressing and storage site enabling signals to the RAM. Boundary detectors monitor the addressing and storage site selection signals to determine whenever storage sites within a new block of storage sites are sought to be addressed. When a boundary transition is detected, a control signal is provided to the vector generator which slows the operation of the vector generator for a period of time sufficient to permit the RAM to accept a new address. For all other addresses, the vector generator is permitted to operate at a higher speed wherein access to the RAM is made by way of enabling specific storage sites within the block of storage sites being written into.

摘要翻译： 一种用于将数据向量高速写入随机存取存储器的方法和装置，其中随机存取存储器（RAM）被划分为可寻址存储位置的块，并且其中每个块内的存储位置是可单独访问的。 向量生成器向RAM提供寻址和存储站点使能信号。 边界检测器监视寻址和存储站点选择信号，以确定寻找新的存储站点内的存储位置。 当检测到边界转变时，向矢量发生器提供控制信号，该矢量发生器使矢量发生器的操作减慢足以允许RAM接受新地址的时间段。 对于所有其他地址，允许向量生成器以更高的速度操作，其中通过使存储位置块内的特定存储位置被写入来进行对RAM的访问。

公开(公告)号：US4279014A

公开(公告)日：1981-07-14

申请号：US933546

申请日：1978-08-14

申请人： Jean-Claude M. Cassonnet ,  Guy Hiot ,  Violette Cohen

发明人： Jean-Claude M. Cassonnet ,  Guy Hiot ,  Violette Cohen

IPC分类号： G06F12/02 ,  G06F12/10 ,  G06F9/20

CPC分类号： G06F12/0292 ,  G06F12/1018

摘要： An arrangement for dynamically translating virtual address into absolute or physical addresses of items of data. Each virtual address includes a segment table number, a segment table entry, and a segment page number. Segment descriptors are stored in a central memory. The address of a particular segment descriptor may be calculated from the segment table number and the segment table entry. From the segment descriptor, a unique identification termed a logic page number may be calculated. The logic page number permits pseudo-associative access to a table containing a number of entries proportional to the number of physical pages of the main memory, allowing the physical address to be determined.

摘要翻译： 用于将虚拟地址动态地转换成数据项的绝对或物理地址的布置。 每个虚拟地址包括段表号，段表条目和段页号。 段描述符存储在中央存储器中。 可以从段表号和段表项计算特定段描述符的地址。 可以从段描述符计算称为逻辑页码的唯一标识。 逻辑页码允许对包含与主存储器的物理页数成比例的多个条目的表的伪相关访问，从而允许确定物理地址。

公开(公告)号：US4224668A

公开(公告)日：1980-09-23

申请号：US864

申请日：1979-01-03

申请人： Arthur Peters ,  Virendra S. Negi

发明人： Arthur Peters ,  Virendra S. Negi

IPC分类号： G06F9/42 ,  G06F9/20

CPC分类号： G06F9/4426

摘要： A control store in a data processor is addressed by means of next address generation logic which includes a first multiplexer utilized to address the control store, which multiplexer has several inputs. One of such inputs is received from a latching mechanism which allows more than one test condition to be simultaneously utilized for addressing the control store on a free flow basis. These test conditions, as well as information from an addressed control word, are utilized in a multiplexed arrangement as one input of the first multiplexer. By use of other inputs of such first multiplexer, the control store may be addressed by use of branch address information, as well as other test condition information. A page register provides the page address, to a plurality of pages included in this control store with the locations in each such page addressed by use of the above noted multiplexer combination.

摘要翻译： 数据处理器中的控制存储器通过下一个地址生成逻辑来寻址，该地址生成逻辑包括用于寻址控制存储器的第一多路复用器，该多路复用器具有多个输入。 从锁定机构接收这样的输入之一，其允许同时利用多于一个的测试条件来以自由流为基础对控制存储器进行寻址。 这些测试条件以及来自寻址的控制字的信息以多路复用方式用作第一多路复用器的一个输入。 通过使用这种第一多路复用器的其他输入，可以通过使用分支地址信息以及其他测试条件信息来寻址控制存储器。 页面寄存器将页面地址提供给包含在该控制存储器中的多个页面，其中通过使用上述复用器组合寻址每个这样的页面中的位置。

公开(公告)号：US4218743A

公开(公告)日：1980-08-19

申请号：US925490

申请日：1978-07-17

申请人： Roy L. Hoffman ,  Glen R. Mitchell ,  Frank G. Soltis

发明人： Roy L. Hoffman ,  Glen R. Mitchell ,  Frank G. Soltis

IPC分类号： G06F12/10 ,  G06F9/20

CPC分类号： G06F12/1018 ,  G06F12/1081

摘要： Address translation apparatus is provided for translating virtual addresses to real storage addresses and real storage addresses to virtual storage addresses. The address translation apparatus uses a page directory having a next real address and an associated virtual address ordered according to real addresses. This simplifies the manner in which the input/output (I/O) handles addressing in a virtual storage computer system. When the I/O device control mechanism needs to resolve the real I/O address register, it uses the contents of that register to index into the page directory to obtain a corresponding virtual address. The corresponding virtual address is incremented and converted to a real address which is used to index into the page directory. The virtual address taken from the page directory is then compared with the virtual address which had been incremented and translated. If the two compare then the real address which had been used to access the page directory is entered into a register so as to be available as a real main storage address. In actuality it is only a partial real main storage address and is concantenated with a byte identifier portion of the main storage address which requires no translation and which was a part of the original I/O real address for main storage.

摘要翻译： 提供地址转换装置，用于将虚拟地址转换为实际存储地址和实际存储地址到虚拟存储地址。 地址转换装置使用具有根据实际地址排序的下一个实际地址和相关联的虚拟地址的页面目录。 这简化了输入/输出（I / O）在虚拟存储计算机系统中处理寻址的方式。 当I / O设备控制机制需要解析实际的I / O地址寄存器时，使用该寄存器的内容将其索引到页面目录中以获取相应的虚拟地址。 相应的虚拟地址递增并转换为用于索引到页面目录中的实际地址。 然后将从页面目录获取的虚拟地址与已经递增和翻译的虚拟地址进行比较。 如果两者比较，那么用于访问页面目录的真实地址被输入到一个寄存器中，以便作为一个真正的主存储地址可用。 实际上，它只是部分实际的主存储地址，并且与主存储地址的字节标识符部分相结合，不需要转换，也是主存储器的原始I / O实地址的一部分。

公开(公告)号：US4215402A

公开(公告)日：1980-07-29

申请号：US953675

申请日：1978-10-23

申请人： Glen R. Mitchell ,  Merle E. Houdek

发明人： Glen R. Mitchell ,  Merle E. Houdek

IPC分类号： G06F12/10 ,  G06F17/30 ,  G06F9/20 ,  G06F13/00

CPC分类号： G06F17/30949 ,  G06F12/1027

摘要： The present invention discloses an apparatus for the efficient translation of virtual addresses to main storage addresses by means of a hash index table which contains main storage addresses. Hash generator apparatus is provided for generating a uniform distribution of hash index table entry addresses from a non-uniform distribution of virtual addresses in a data processing system, where the size of the hash index table is variable and is based on the size of main storage. A field of bits within the virtual address corresponding to the page identification bits are reversed in order and aligned with two groups of bits from a field of bits within the virtual address corresponding to object identification bits, and the three groups of bits are applied to an EXCLUSIVE-OR circuit. The alignment of the three groups of bits and the size of the hash index table entry addresses generated by the present invention are based on the size of the hash index table.

摘要翻译： 本发明公开了一种通过包含主存储地址的散列索引表将虚拟地址有效地转换为主存储地址的装置。 哈希发生器装置被提供用于从数据处理系统中的虚拟地址的不均匀分布产生哈希索引表入口地址的均匀分布，其中散列索引表的大小是可变的，并且基于主存储器的大小 。 对应于页面标识位的虚拟地址内的比特字段按顺序颠倒，并且与来自对应于对象标识位的虚拟地址内的比特位的两组比特对齐，并且将三组比特应用于 EXCLUSIVE-OR电路。 本发明生成的三组比特的对齐和散列索引表入口地址的大小基于散列索引表的大小。

公开(公告)号：US4187539A

公开(公告)日：1980-02-05

申请号：US819868

申请日：1977-07-28

申请人： John R. Eaton

发明人： John R. Eaton

IPC分类号： G06F9/22 ,  G06F9/28 ,  G06F9/38 ,  G06F9/20 ,  G06F9/06

CPC分类号： G06F9/3867

摘要： A pipelined data processing system having n processing stages, each of which is under the control of a central microprogram. Each microprogram instruction is decoded to produce n control signals, one for each processing stage. Microprogram start addresses are generated by combining information from the latest n program instructions received. Thus, each microprogram sequence implements a combination of phases of successive program instructions. A flag register is used to store relatively static control information, and effectively provides an extension of the microprogram instruction.

摘要翻译： 具有n个处理阶段的流水线数据处理系统，每个处理阶段处于中央微程序的控制之下。 每个微程序指令被解码以产生n个控制信号，每个处理阶段一个。 通过组合来自最新的n个程序指令的信息来生成微程序起始地址。 因此，每个微程序序列实现连续程序指令的相位组合。 标志寄存器用于存储相对静态的控制信息，有效地提供了微程序指令的扩展。

公开(公告)号：US4181939A

公开(公告)日：1980-01-01

申请号：US866015

申请日：1977-12-30

申请人： Francis T. Lyons

发明人： Francis T. Lyons

IPC分类号： G01T1/161 ,  G01T1/29 ,  G06T11/00 ,  G06F9/20 ,  G06F3/00

CPC分类号： G06T11/005 ,  A61B6/037 ,  G01T1/2985

摘要： Device for providing communication between a radiation detector array and a general purpose computer and to receive accumulated scintillation counts from the array of detectors and deposit the same in computer memory in a manner which minimizes subsequent data manipulation.

摘要翻译： 用于在辐射检测器阵列和通用计算机之间提供通信的装置，以及从所述检测器阵列接收累积的闪烁计数并以使所述后续数据操作最小化的方式将其沉积在计算机存储器中。

公开(公告)号：US4179731A

公开(公告)日：1979-12-18

申请号：US784459

申请日：1977-04-04

申请人： Isamu Yamazaki

发明人： Isamu Yamazaki

IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/26 ,  G06F9/32 ,  G06F9/38 ,  G06F9/16 ,  G06F9/20

CPC分类号： G06F9/267

摘要： A microprogrammed control system comprises: a memory for storing a microprogram programmed with microinstructions; a memory for storing microinstructions for branching microinstruction; an address register for storing the address of the microinstruction to be next executed; and a microinstruction register for storing the microinstruction to be executed. The program operation of the microprogrammed control system depends on whether the micro-instruction stored in the microinstruction register is the branching one or not. In the case of non-branching microinstruction, the operation of ordinary microinstructions is executed. In the case of branching microinstruction, a special operation is executed for making the operation of the branching microinstruction equivalent to that of the ordinary microinstruction.

摘要翻译： 微程序控制系统包括：存储器，用于存储用微指令编程的微程序; 用于存储分支微指令的微指令的记忆体; 用于存储要下一次执行的微指令的地址的地址寄存器; 以及用于存储要执行的微指令的微指令寄存器。 微程序控制系统的程序操作取决于存储在微指令寄存器中的微指令是否分支。 在非分支微指令的情况下，执行普通微指令的操作。 在分支微指令的情况下，执行特殊操作以使分支微指令的操作等同于普通微指令。

公开(公告)号：US4168523A

公开(公告)日：1979-09-18

申请号：US858050

申请日：1977-12-06

申请人： Venu Chari ,  Ronald L. Engelbrecht

发明人： Venu Chari ,  Ronald L. Engelbrecht

IPC分类号： G06F9/26 ,  G06F9/20

CPC分类号： G06F9/265

摘要： A data processor utilizes a central processor controller to determine selectively the next required operation phase while executing a current operation phase. Control words contained in a second stage control memory are selectively addressed from addresses contained in a first stage control memory. The selection of a particular address of a control word contained in said first stage control memory is determined from combinations of signals received by a condition multiplexer interposed between said first and second stage control memories, portions of program instructions contained in main memory, externally operated manual switches, and various internal control flags. The operation phase is defined as an operation, which is defined by said control word. The generation of the address for the next required control word and the execution of the operation defined by the current control word occurs in the same machine cycle. Each control word comprises a mode of operation, control signals for the various execute units, and input signals for the condition multiplexer for determining the next operation phase control word address, required by the data processor in the process of executing program instructions contained in the data processor's main memory.

摘要翻译： 数据处理器利用中央处理器控制器在执行当前操作阶段期间选​​择性地确定下一个所需的操作阶段。 包含在第二级控制存储器中的控制字被选择性地从包含在第一级控制存储器中的地址寻址。 包含在所述第一级控制存储器中的控制字的特定地址的选择由插入在所述第一和第二级控制存储器之间的条件复用器接收的信号的组合，主存储器中包含的程序指令的部分，外部操作的手册 开关和各种内部控制标志。 操作阶段被定义为由所述控制字定义的操作。 下一个所需控制字的地址的生成和由当前控制字定义的操作的执行在同一机器周期中发生。 每个控制字包括操作模式，用于各种执行单元的控制信号，以及用于条件多路复用器的输入信号，用于确定数据处理器在执行数据中包含的程序指令的过程中所需的下一个操作相位控制字地址 处理器的主要内存。