再颁专利
USRE36027E Random access memory of a CSL system with a bit line pair and an I/O
line pair independently set to different precharge voltages
失效
具有位线对和独立设置为不同预充电电压的I / O线对的CSL系统的随机存取存储器
- 专利标题： Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages
- 专利标题（中）： 具有位线对和独立设置为不同预充电电压的I / O线对的CSL系统的随机存取存储器
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申请号： US664081申请日： 1996-06-13
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公开(公告)号： USRE36027E公开(公告)日： 1999-01-05
- 发明人: Kazutami Arimoto , Kazuyasu Fujishima , Hideto Hidaka , Masaki Tsukude , Tsukasa Ohishi
- 申请人： Kazutami Arimoto , Kazuyasu Fujishima , Hideto Hidaka , Masaki Tsukude , Tsukasa Ohishi
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX3-106789 19910409
- 主分类号： G11C11/409
- IPC分类号： G11C11/409 ; G11C7/10 ; G11C7/12 ; G11C11/401 ; G11C11/4094 ; G11C11/4096 ; G11C11/41 ; H01L27/10 ; G11C7/00
摘要：
In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.
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