公开(公告)号：US07233382B2

公开(公告)日：2007-06-19

申请号：US10793007

申请日：2004-03-05

申请人： Yasuhisa Yamaji ,  Yasunori Chikawa ,  Tsukasa Ohishi

发明人： Yasuhisa Yamaji ,  Yasunori Chikawa ,  Tsukasa Ohishi

IPC分类号： G02F1/1345

CPC分类号： G02F1/13452 ,  G02F2001/133342 ,  H04M2250/16 ,  H05K1/147

摘要： This invention is to provide a liquid crystal module that enables a liquid crystal display (LCD) device to be further miniaturized. The liquid crystal module is configured to include at least two LCD devices and formed separately from each other, a first flexible substrate on which a semiconductor chip for driving the LCD devices and is mounted, and a second flexible substrate wherein signal transmission wiring is formed. One of the LCD devices and is electrically connected to the first flexible substrate, the other one of the LCD devices and is electrically connected to the second flexible substrate, and the first flexible substrate is electrically connected to the second flexible substrate.

摘要翻译： 本发明是提供一种能够使液晶显示（LCD）装置进一步小型化的液晶模块。 液晶模块被配置为包括至少两个LCD装置并且彼此分开形成，其上安装用于驱动LCD装置的半导体芯片和其上形成有信号传输布线的第二柔性基板的第一柔性基板。 LCD器件中的一个并且电连接到第一柔性衬底，另一个LCD器件并且电连接到第二柔性衬底，并且第一柔性衬底电连接到第二柔性衬底。

公开(公告)号：USRE36027E

公开(公告)日：1999-01-05

申请号：US664081

申请日：1996-06-13

申请人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

发明人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1048

摘要： In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

摘要翻译： 在CSL系统的动态RAM中，存储器阵列被分成多个存储器阵列部分，并且设置在各个存储器阵列部分中的位线对响应于CSL输出而同时连接到它们对应的I / O线对 。 在这样的RAM中，只有要访问的存储器阵列部分的I / O线对被预充电到VCC-Vth的电平，而不存储阵列部分的I / O线对被预充电到 + E，fra 1/2 + EE xVCC的电平与位线对相同。 这使得可以实现更快的数据读取操作，并且还防止不必要的电流在未加工的存储器阵列部分中的位线对和I / O线对之间流动。

公开(公告)号：US5321657A

公开(公告)日：1994-06-14

申请号：US865145

申请日：1992-04-08

申请人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

发明人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1048

摘要： In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

摘要翻译： 在CSL系统的动态RAM中，存储器阵列被分成多个存储器阵列部分，并且设置在各个存储器阵列部分中的位线对响应于CSL输出而同时连接到它们对应的I / O线对 。 在这样的RAM中，只有要访问的存储器阵列部分的I / O线对被预充电到VCC-Vth的电平，而不存储阵列部分的I / O线对被预充电到 1 / 2xVCC的电平与位线对相同。 这使得可以实现更快的数据读取操作，并且还防止不必要的电流在未加工的存储器阵列部分中的位线对和I / O线对之间流动。