再颁专利
- 专利标题： Method and mechanism for implementing electronic designs having power information specifications background
- 专利标题（中）： 实现具有电力信息规格背景的电子设计的方法和机制
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申请号： US13494363申请日： 2012-06-12
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公开(公告)号： USRE44479E1公开(公告)日： 2013-09-03
- 发明人: Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghoa Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher , Mitchell W. Hines
- 申请人： Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghoa Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher , Mitchell W. Hines
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Schwegman Lundberg & Woessner, P.A.
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.
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