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    System and method for audio/video synchronization
    1.
    发明授权
    System and method for audio/video synchronization 有权
    用于音频/视频同步的系统和方法

    公开(公告)号：US08995536B2

    公开(公告)日：2015-03-31

    申请号：US10892897

    申请日：2004-07-16

    Applicant: Mk Subramanian ,  Sandeep Bhatia ,  Santosh Savekar ,  Gaurav Aggarwal ,  K. Shivapirakasan

    Inventor： Mk Subramanian ,  Sandeep Bhatia ,  Santosh Savekar ,  Gaurav Aggarwal ,  K. Shivapirakasan

    IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N21/44 ,  H04N21/43

    CPC classification number: H04N21/44004 ,  H04N21/4307

    Abstract: Described herein is a system and method for audio visual synchronization. The picture are displayed by receiving an identifier, said identifier associated with a frame buffer storing a picture; extracting a presentation time stamp associated with the picture, wherein the picture is associated with a time stamp; comparing a local time clock value to the presentation time stamp; determining that the picture is mature for presentation if the presentation time stamp exceeds the local time clock value by less than a first predetermined threshold; and determining that the picture is mature for presentation if the local time clock value exceeds the presentation time stamp by less than a second predetermined threshold.

    Abstract translation: 这里描述了一种用于视听同步的系统和方法。 通过接收标识符显示图像，所述标识符与存储图像的帧缓冲器相关联; 提取与所述图片相关联的呈现时间戳，其中所述图片与时间戳相关联; 将本地时钟值与演示时间戳进行比较; 如果所述呈现时间戳超过所述本地时间时钟值小于第一预定阈值，则确定所述图片是成熟的; 以及如果所述本地时间时钟值超过所述呈现时间戳小于第二预定阈值，则确定所述图片是否成熟以进行呈现。

    Method and system for attending a meeting
    3.
    发明授权
    Method and system for attending a meeting 有权
    出席会议的方式和制度

    公开(公告)号：US08527287B1

    公开(公告)日：2013-09-03

    申请号：US12247804

    申请日：2008-10-08

    Applicant: Sandeep Bhatia

    Inventor： Sandeep Bhatia

    IPC: G06Q10/00

    CPC classification number: G06Q10/109 ,  H04L12/1818 ,  H04M3/567

    Abstract: The invention relates to a method for attending a meeting. The method involves determining the presence of a meeting notice for a meeting in meeting software, where the meeting notice comprises a start time, a end time, a name of an attendee, and information to connect to the meeting. The method also involves obtaining information about the meeting from the meeting notice to populate a meeting template, determining that the meeting is a not-in-person meeting, and populating the meeting template to obtain a meeting record for the meeting. The method also involves connecting over a voice communication channel to the meeting at the start time using the information in the meeting record for the meeting and terminating the meeting at the end time of the meeting.

    Abstract translation: 本发明涉及一种出席会议的方法。 该方法涉及确定在会议软件中会议通知的存在，会议通知包括开始时间，结束时间，参加者的姓名以及连接到会议的信息。 该方法还包括从会议通知中获取有关会议的信息，填写会议模板，确定会议是非会议人员会议，填写会议模板以获取会议记录。 该方法还包括在开始时使用会议记录中的信息在语音通信频道上连接会议，并在会议结束时终止会议。

    Delta frame buffers
    4.
    发明授权
    Delta frame buffers 有权
    Delta帧缓冲区

    公开(公告)号：US08488665B2

    公开(公告)日：2013-07-16

    申请号：US10606216

    申请日：2003-06-25

    Applicant: Srinivasa Mogathala Prabhakara Reddy ,  Sandeep Bhatia ,  Srilakshmi Dorarajulu

    Inventor： Srinivasa Mogathala Prabhakara Reddy ,  Sandeep Bhatia ,  Srilakshmi Dorarajulu

    IPC: H04N7/12

    CPC classification number: H04N19/00569 ,  H04N19/427 ,  H04N19/50

    Abstract: Presented herein is a system and method for reducing the total size of the frame buffer portion of a decoding circuit. The reduction in size is possible because first portions of B-pictures are displayed while second portions occurring later in the raster order are decoded. The foregoing allows the second portions occurring later in the raster order to overwrite third portions of the picture that have already been displayed. As a result, the frame buffer for providing the frame from a decoder to the display engine need only store the portion that is being displayed and the portion that is being decoded.

    Abstract translation: 这里提出的是用于减小解码电路的帧缓冲器部分的总大小的系统和方法。 尺寸的减小是可能的，因为B图像的第一部分被显示，而以光栅顺序发生的第二部分被解码。 上述允许以光栅顺序稍后出现的第二部分覆盖已经显示的图片的第三部分。 结果，用于将帧从解码器提供给显示引擎的帧缓冲器仅需要存储正被显示的部分和正被解码的部分。

    Scan testing architectures for power-shutoff aware systems
    5.
    发明授权
    Scan testing architectures for power-shutoff aware systems 有权
    扫描测试架构，用于断电感知系统

    公开(公告)号：US08001433B1

    公开(公告)日：2011-08-16

    申请号：US12345950

    申请日：2008-12-30

    Applicant: Sandeep Bhatia ,  Patrick Gallagher ,  Brian Foutz ,  Vivek Chickermane

    Inventor： Sandeep Bhatia ,  Patrick Gallagher ,  Brian Foutz ,  Vivek Chickermane

    IPC: G01R31/28 ,  G06F17/50

    CPC classification number: G01R31/318575 ,  G01R31/318563

    Abstract: In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments. A decompressor circuit receives a decompressor input and is operatively connected to the scan-segment input ends, and a compressor circuit is operatively connected to the scan segment output ends and generates a compressor output. Isolation circuits at scan-segment exits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.

    Abstract translation: 在适于扫描测试的电路中，第一组连接将电路元件配置成具有单独的功率电平控制的电源域，并且第二组连接将电路元件配置为形成用于从输入端将值加载到电路元件中的扫描段 的扫描段和从扫描段输出端的电路元件卸载值。 解压缩器电路接收解压缩器输入并且可操作地连接到扫描段输入端，并且压缩机电路可操作地连接到扫描段输出端并产生压缩器输出。 扫描段出口处的隔离电路在相应的独立电源域处于关机状态时，为扫描段出口处的扫描段设置值。

    Low power scan test for integrated circuits
    9.
    发明授权
    Low power scan test for integrated circuits 有权
    集成电路的低功耗扫描测试

    公开(公告)号：US07693676B1

    公开(公告)日：2010-04-06

    申请号：US11704443

    申请日：2007-02-09

    Applicant: Brion L. Keller ,  Vivek Chickermane ,  Sandeep Bhatia

    Inventor： Brion L. Keller ,  Vivek Chickermane ,  Sandeep Bhatia

    IPC: G01R27/28

    CPC classification number: G01R31/318575

    Abstract: Low power design is a critical concern and metric for integrated circuits. During scan based manufacturing test, electric power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test. Excessive electric power dissipation during scan test can result in excessive voltage variations, reduced noise margins and other signal integrity issues which could invalidate the test or may lead to premature chip failure. Power dissipation during test is minimized by selecting particular values for the unused care-bits in values of the test vectors on a probabilistic basis to minimize switching, while preserving test vector quality.

    Abstract translation: 低功耗设计是集成电路的关键和指标。 在基于扫描的制造测试中，由于芯片可能未被设计为在扫描测试期间容忍过度的切换，因此电功耗变得更加重要。 扫描测试期间过大的电力消耗可能会导致过大的电压变化，降低的噪声容限和其他信号完整性问题，这可能使测试无效或可能导致芯片过早失效。 通过在概率基础上选择测试向量值中未使用的关心位的特定值来最小化测试期间的功耗，同时保持测试矢量质量。

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