A data processing system has a CPU (36) linked via a unidirectional read bus (42) and a unidirectional write and address bus (44) to a data memory (e.g. cache, RAM or disc), in the form of a cache memory (40). Since the read bus and the write and address bus are only driven in one direction, lost time through reversing the direction of signal travel along a bus is avoided. Read-data words (RD) and instruction-data words (I) are transferred from the cache memory to a core (38) of the CPU via the read bus. Instruction-address (PC), read-address (RA), write-addresses (WA) and write-data words (WD) are time division multiplexed on the write and address bus to pass from the core to the cache memory. The system supports burst mode transfer thereby reducing the number of addresses that need to be transferred on the write and address bus thereby releasing bandwidth on this bus for use by write-data words.