公开(公告)号：WO1998012624A1

公开(公告)日：1998-03-26

申请号：PCT/GB1997002257

申请日：1997-08-22

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian ,  GLASS, Simon, James

IPC: G06F09/30

CPC classification number: G06F7/57 ,  G06F7/49921 ,  G06F7/49994 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/3877

Abstract: A data processing system is provided including an arithmetic logic unit (20, 22, 24) receiving input operands from M X-bit registers to produce output data words stored within N Y-bit registers, where M/N = 3,8

Abstract translation: 提供了一种数据处理系统，包括从M×位寄存器接收输入操作数的算术逻辑单元（20,22,24），以产生存储在N个Y位寄存器内的输出数据字，其中M / N = = YX

公开(公告)号：WO1998012625A1

公开(公告)日：1998-03-26

申请号：PCT/GB1997002258

申请日：1997-08-22

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  YORK, Richard ,  FRANCES, Hedley, James ,  SYMES, Dominic ,  BILES, Stuart

IPC: G06F09/30

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/30079 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30134 ,  G06F9/325 ,  G06F9/3824 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: The present invention provides a data processing apparatus comprising: a plurality of registers for storing data items to be processed; a processor for processing instructions to be applied to data items stored in said plurality of registers; and register remapping logic for converting a logical register reference within a preselected set of instructions to a physical register reference identifying the register containing the data item required for processing by the processor. By this approach, a remapping instruction need only be executed once in order for the remapping to be applied to a desired number of instructions. This is in contrast to prior art techniques, where subsequent to a remapping instruction being executed, the remapping is applied to all subsequent instructions, i.e. a desired number of instructions cannot be selected. The invention is particularly advantageously employed in apparatus arranged to repeat an instruction loop, the instruction loop including said preselected set of instructions. In such cases, loop hardware used to manage the repeat instruction can be arranged to update the register remapping logic each time the instruction loop is repeated, and hence the remapping instruction used to configure the register remapping logic is only executed once prior to the repeat instruction being executed.

Abstract translation: 本发明提供一种数据处理装置，包括：多个用于存储要处理的数据项的寄存器; 处理器，用于处理要应用于存储在所述多个寄存器中的数据项的指令; 以及注册重映射逻辑，用于将预选指令集中的逻辑寄存器参考转换为识别包含由处理器处理所需的数据项的寄存器的物理寄存器引用。 通过这种方法，重新映射指令只需要执行一次，以便将重映射应用于期望数量的指令。 这与现有技术相反，其中在执行重新映射指令之后，将重映射应用于所有后续指令，即不能选择期望数量的指令。 本发明特别有利地用于设置为重复指令循环的装置，该指令循环包括所述预选指令集。 在这种情况下，可以设置用于管理重复指令的环路硬件，以在每次重复指令循环时更新寄存器重映射逻辑，因此用于配置寄存器重映射逻辑的重新映射指令仅在重复指令之前执行一次 被执行

公开(公告)号：WO1998015893A1

公开(公告)日：1998-04-16

申请号：PCT/GB1997002694

申请日：1997-09-30

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  DAY, Paul ,  PAVER, Nigel, Charles

IPC: G06F09/38

CPC classification number: G06F9/30083 ,  G06F1/32 ,  G06F9/30079 ,  G06F9/3869 ,  G06F9/3871

Abstract: The present invention provides an apparatus and method for processing data, the apparatus comprising a plurality of asynchronous control circuits, each asynchronous control circuit employing a request-acknowledge control loop to control data flow within that asynchronous control circuit, and being arranged to exchange data signals with at least one other of said plurality of asynchronous control circuits. Further, a first of said asynchronous control circuits includes a halt circuit for blocking a control signal in the control loop of the first asynchronous control circuit, thereby preventing the exchange of data signals with said at least one other of said plurality of asynchronous control circuits so as to cause the control loops of said plurality of asynchronous control circuits to become blocked. The present invention is based on an asynchronous design, which only causes transitions in the circuit in response to a request to carry out useful work. It can switch instantaneously between zero power dissipation and maximum performance upon demand. According to the invention, there is provided a 'Halt' circuit which causes all processor activity to cease until an interrupt occurs. The circuit preferably works by intercepting a control signal in the processing apparatus' asynchronous control circuits, effectively breaking a single request-acknowledge control loop. Since the control circuits are interrelated, blocking the response in one loop rapidly (but not instantaneously) stalls all the other control loops in the apparatus, and hence the stall ultimately propagates throughout the entire apparatus, terminating all activity. Preferably, an interrupt is used to release the stall in the original control loop, and activity then propagates from this point throughout the system.

Abstract translation: 本发明提供了一种用于处理数据的装置和方法，该装置包括多个异步控制电路，每个异步控制电路采用一个请求确认控制环来控制该异步控制电路内的数据流，并且被配置为交换数据信号 与所述多个异步控制电路中的至少另一个异步控制电路。 此外，所述异步控制电路中的第一个包括用于阻塞第一异步控制电路的控制环路中的控制信号的停止电路，从而防止与所述多个异步控制电路中的所述至少另一个异步控制电路的数据信号的交换 以致所述多个异步控制电路的控制环路被阻塞。 本发明基于异步设计，其仅响应于执行有用工作的请求而引起电路中的转换。 它可以根据需要在零功耗和最大性能之间瞬间切换。 根据本发明，提供了一种“停止”电路，其使所有处理器的活动停止，直到发生中断。 该电路优选通过截取处理装置的异步控制电路中的控制信号而有效地破坏单个请求确认控制环路。 由于控制电路是相互关联的，所以在一个环路中快速（但不是瞬间）阻塞响应使设备中的所有其他控制环停止，因此失速最终在整个设备中传播，从而终止所有的活动。 优选地，使用中断来释放原始控制回路中的停顿，然后从整个系统的这一点传播活动。

公开(公告)号：WO1998012628A1

公开(公告)日：1998-03-26

申请号：PCT/GB1997002261

申请日：1997-08-22

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian ,  GLASS, Simon, James

IPC: G06F09/302

CPC classification number: G06F9/30112 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30127 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/30185 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A data processing system having a plurality of registers (10) and an arithmetic logic unit (20, 22, 24) is responsive to program instruction words. At least one program instruction word includes a destination register bit field specifying a destination register of a result data word and a destination register write disable flag for disabling writing of that result data word to the destination register.

Abstract translation: 具有多个寄存器（10）和算术逻辑单元（20,22,24）的数据处理系统响应于程序指令字。 至少一个程序指令字包括指定结果数据字的目的地寄存器的目标寄存器位字段和用于禁止将该结果数据字写入到目标寄存器的目的寄存器写禁止标志。

公开(公告)号：WO1998014864A1

公开(公告)日：1998-04-09

申请号：PCT/GB1997001812

申请日：1997-07-04

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  LIU, Jianwei

IPC: G06F07/50

CPC classification number: G06F7/506 ,  G06F7/507 ,  G06F2207/3876

Abstract: A binary adder circuit includes carry evaluation circuits that encode a carry production control signal using two signal values (V, W) such that V = W = 0 indicates a carry kill, V = W = 1 indicates a carry generate and V =/ W indicates a carry propagate. The carry evaluation circuit may be implemented in static or dynamic CMOS logic.

Abstract translation: 二进制加法器电路包括使用两个信号值（V，W）对携带产生控制信号进行编码的进位评估电路，使得V = W = 0表示进位中断，V = W = 1表示进位产生，V = / W 表示进位传播。 进位评估电路可以在静态或动态CMOS逻辑中实现。

公开(公告)号：WO1998012627A1

公开(公告)日：1998-03-26

申请号：PCT/GB1997002260

申请日：1997-08-22

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian ,  GLASS, Simon, James

IPC: G06F09/302

CPC classification number: G06F9/30014 ,  G06F7/48 ,  G06F9/30025 ,  G06F9/30036

Abstract: A data processing system having a plurality of registers (10) and an arithmetic logic unit (20, 22, 24) includes program instruction words having a source register bit field Sn specifying one of the registers storing an input operand data word together with an input operand size flag indicating whether the input operand has a N-bit size or (N/2)-bit size together with a high/low location flag indicating which of the high order bit positions or low order bit positions stores the input operand if it is of the smaller size. It is preferred that the arithmetic logic unit is also able to perform parallel operation program instruction words operating independently upon (N/2)-bit input operand data words stored in respective halves of a register.

Abstract translation: 具有多个寄存器（10）和算术逻辑单元（20,22,24）的数据处理系统包括具有源寄存器位字段Sn的程序指令字，其指定存储输入操作数数据字的寄存器之一以及输入 指示输入操作数是否具有N位大小或（N / 2）位大小以及指示高位位置或低位位置存储输入操作数的高/低位置标志，如果它 尺寸较小。 优选地，算术逻辑单元还能够执行独立于存储在寄存器的相应两半中的（N / 2）位输入操作数数据字独立运行的并行操作程序指令字。

公开(公告)号：WO1997037341A1

公开(公告)日：1997-10-09

申请号：PCT/GB1997000457

申请日：1997-02-19

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  FLYNN, David, Walter ,  STEVENS, Ashley, Miles ,  HOWARTH, Lance, Gregory

IPC: G09G05/06

CPC classification number: G09G5/06

Abstract: A display palette system comprising a digital palette (16) supplied with frames of data (26). Each frame of data (26) includes a complete set of palette mapping data and control data (28) with which the digital palette (16) is programmed under control of a palette control circuit (24). The rows of logical pixel data that follow in the frame each terminate with row palette data (RP) that can be directed to reprogram the digital palette (16) part of the way through the display of a single frame.

Abstract translation: 一种显示调色板系统，包括提供有数据帧（26）的数字调色板（16）。 每个数据帧（26）包括一组调色板映射数据和控制数据（28），数字调色板（16）在调色板控制电路（24）的控制下被编程。 在帧中跟随的逻辑像素数据行各自以行调色板数据（RP）终止，该调色板数据可以被引导以通过单个帧的显示部分地重新编程数字调色板（16）。

公开(公告)号：WO1995029441A1

公开(公告)日：1995-11-02

申请号：PCT/GB1995000229

申请日：1995-02-06

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  SEGARS, Simon, Anthony

IPC: G06F11/00

CPC classification number: G06F11/3656 ,  G06F11/2236

Abstract: A data processing apparatus comprising an integrated circuit (2) having a processor core (4) surrounded by a scan chain (10) is described. The processor core (4) can execute program instructions using either a system clock signal MClk or a test clock signal DClk. A clock selecting bit S within the program instructions for test operation indicates which clock is to be used and a clock selecting mechanism (12, 14) selects the indicated clock signal and passes this to the processor core (4). When the system clock MClk is selected execution of the program instruction by the processor core (4) may be coordinated with the operation of connected auxiliary circuits such as a DRAM (6).

Abstract translation: 描述了包括具有由扫描链（10）围绕的处理器核心（4）的集成电路（2）的数据处理装置。 处理器核心（4）可以使用系统时钟信号MClk或测试时钟信号DClk来执行程序指令。 用于测试操作的程序指令内的时钟选择位S指示要使用哪个时钟，时钟选择机构（12,14）选择指示的时钟信号并将其传递给处理器核心（4）。 当选择系统时钟MClk时，由处理器核心（4）执行程序指令可以与诸如DRAM（6）的连接的辅助电路的操作协调。

公开(公告)号：WO1995019004A1

公开(公告)日：1995-07-13

申请号：PCT/GB1994002254

申请日：1994-10-14

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  FURBER, Stephen, Byram ,  OLDFIELD, William, Henry

IPC: G06F13/42

CPC classification number: G06F9/3802 ,  G06F9/3824 ,  G06F13/4234 ,  G06F13/4239

Abstract: A data processing system has a CPU (36) linked via a unidirectional read bus (42) and a unidirectional write and address bus (44) to a data memory (e.g. cache, RAM or disc), in the form of a cache memory (40). Since the read bus and the write and address bus are only driven in one direction, lost time through reversing the direction of signal travel along a bus is avoided. Read-data words (RD) and instruction-data words (I) are transferred from the cache memory to a core (38) of the CPU via the read bus. Instruction-address (PC), read-address (RA), write-addresses (WA) and write-data words (WD) are time division multiplexed on the write and address bus to pass from the core to the cache memory. The system supports burst mode transfer thereby reducing the number of addresses that need to be transferred on the write and address bus thereby releasing bandwidth on this bus for use by write-data words.

Abstract translation: 数据处理系统具有通过单向读取总线（42）和单向写入和地址总线（44）连接到高速缓存存储器形式的数据存储器（例如高速缓存，RAM或盘）的CPU（36） 40）。 由于读总线和写地址总线仅在一个方向上驱动，所以避免了沿着总线反转信号行进方向的丢失时间。 读数据字（RD）和指令数据字（I）经由读总线从高速缓冲存储器传送到CPU的核心（38）。 指令地址（PC），读地址（RA），写地址（WA）和写数据字（WD）在写和地址总线上进行时分复用，以从内核传递到高速缓冲存储器。 系统支持突发模式传输，从而减少在写和地址总线上需要传送的地址数量，从而释放该总线上的带宽，以供写入数据字使用。

公开(公告)号：WO1995006287A1

公开(公告)日：1995-03-02

申请号：PCT/GB1994001712

申请日：1994-08-04

Applicant: ADVANCED RISC MACHINES LIMITED ,  FLYNN, David, Walter

Inventor： ADVANCED RISC MACHINES LIMITED

IPC: G06F13/42

CPC classification number: G06F13/1631 ,  G06F12/0879 ,  G06F13/28 ,  G06F13/4243

Abstract: Apparatus for data processing (2) is described employing a common data bus (4) to interconnect a bus master circuit (6) with one or more bus slave circuits (8, 10, 12). The data processing apparatus (2) is configured to support burst mode transfers in which an address word is followed by a sequence of data words relating to addresses following on from that specified by the address word. Such transfers increase the number of data words transmitted per address word that need be specified. The data bus (4) includes an address request signal line (16) by which any of the bus slave circuits (8, 10, 12) may request an address word to be transmitted in the next processing cycle rather than a data word. In this way, the bus master circuit (6) need not be specifically adapted for the bus slaves that are attached to the bus (4), since the bus slaves can themselves indicate to what extent they are able to deal with burst mode transfers. A wait cycle request signal and a signal combination indicating that a burst mode transfer should be completely aborted are also supported.

Abstract translation: 使用公共数据总线（4）描述用于数据处理（2）的装置，以将总线主电路（6）与一个或多个总线从电路（8,10,12）相互连接。 数据处理装置（2）被配置为支持突发模式传输，其中地址字之后是与由地址字指定的跟随的地址相关的数据字序列。 这样的传输增加了需要指定的每个地址字传输的数据字的数量。 数据总线（4）包括地址请求信号线（16），通过该地址请求信号线（16），总线从电路（8,10,12）可以在下一个处理周期而不是数据字中请求要发送的地址字。 以这种方式，总线主电路（6）不需要特别适用于连接到总线（4）的总线从器件，因为总线从器件本身可以指示它们在多大程度上能够处理突发模式传输。 还支持等待周期请求信号和指示突发模式传输应该完全中止的信号组合。