A method for plating an integrated circuit package (10). The method includes constructing a package (10) which has a plurality of internal bond fingers (40) that are subsequently coupled to an inegrated circuit (18). The package contains a plurality of vias that are electrically connected to the bond fingers (40). The vias (32) are also coupled to a layer of metallization (84) as a plating bar to plate the internal bond fingers (40). After plating, the metallization layer (84) is etched from the surface (16) of the package (10).