公开(公告)号：WO1998010625A1

公开(公告)日：1998-03-12

申请号：PCT/US1997011170

申请日：1997-06-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BANERJEE, Koushik ,  CHRONEOS, Robert, J., Jr. ,  MOZDZEN, Tom

IPC: H05K00/00

CPC classification number: H01L24/49 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method for plating an integrated circuit package (10). The method includes constructing a package (10) which has a plurality of internal bond fingers (40) that are subsequently coupled to an inegrated circuit (18). The package contains a plurality of vias that are electrically connected to the bond fingers (40). The vias (32) are also coupled to a layer of metallization (84) as a plating bar to plate the internal bond fingers (40). After plating, the metallization layer (84) is etched from the surface (16) of the package (10).

Abstract translation: 一种用于电镀集成电路封装（10）的方法。 该方法包括构造具有随后耦合到集成电路（18）的多个内部键合指（40）的封装（10）。 该封装包含电连接到接合指状物（40）的多个通孔。 通孔（32）还耦合到作为电镀条的金属化层（84），以平坦化内部粘结指状物（40）。 电镀后，从封装（10）的表面（16）蚀刻金属化层（84）。

公开(公告)号：WO1998010466A1

公开(公告)日：1998-03-12

申请号：PCT/US1997011890

申请日：1997-07-09

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BANERJEE, Koushik ,  CHRONEOS, Robert, J., Jr. ,  MOZDZEN, Tom

IPC: H01L23/48

CPC classification number: H01L23/24 ,  H01L23/057 ,  H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An integrated circuit package (10) which contains an integrated circuit (18). The internal integrated circuit is coupled to external lands (34) located on a first outer surface of the package (10) by a plurality of vias (32). The vias (32) extend through the package (10) from the first outer surface to an opposite second outer surface. The package (10) has a plurality of devices such as capacitors (28) that are mounted to the second outer surface. Some of the vias (32) are connected to a whole group of external lands (34). Grouping the lands (34) to a single via reduces the number of vias (32) on the second surface of the package (10). The reduction in vias (32) allows additional capacitors (28) to be mounted to the second surface of the package (10).

Abstract translation: 一种集成电路封装（10），其包含集成电路（18）。 内部集成电路通过多个通孔（32）耦合到位于封装（10）的第一外表面上的外部焊盘（34）。 通孔（32）从第一外表面延伸穿过包装（10）到相对的第二外表面。 封装（10）具有多个装置，例如安装到第二外表面的电容器（28）。 一些通孔（32）连接到一整组外部焊盘（34）。 将焊盘（34）分组到单个通孔减少了封装（10）的第二表面上的通孔（32）的数量。 通孔（32）的减少允许附加电容器（28）安装到封装（10）的第二表面。

公开(公告)号：WO1998010630A1

公开(公告)日：1998-03-12

申请号：PCT/US1997011277

申请日：1997-06-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BANERJEE, Koushik ,  CHRONEOS, Robert, J., Jr. ,  MOZDZEN, Tom

IPC: H05K07/20

CPC classification number: H01L23/642 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An integrated circuit package (10). The package includes a substrate (12) that has a first internal conductive bus (72) and a second internal conductive bus (74) that are located on a common layer of the substrate and dedicated to different power voltage levels. The busses are coupled to external lands located on a first surface (14) of the package by vias (32) that extend through the substrate. The first and second busses are located on a common layer of the substrate. The package contains an integrated circuit (18) which is mounted to a heat slug (22) that is attached to a second surface of the package. The integrated circuit is coupled to bond fingers located on a shelf of the substrate. Some of the bond fingers (40) are connected to the internal busses by conductive strips (68) that wrap around the edges of the shelf. Some of the vias are connected to a whole group of external lands. Grouping the lands (34g) to a single via reduces the number of vias on the second surface of the package. The reduction in vias allows additional capacitors (28) to be mounted to the second surface of the package.

Abstract translation: 集成电路封装（10）。 封装包括具有位于衬底的公共层上并专用于不同功率电压电平的第一内部导电总线（72）和第二内部导电总线（74）的衬底（12）。 总线通过延伸穿过衬底的通孔（32）耦合到位于封装的第一表面（14）上的外部焊盘。 第一和第二总线位于基板的公共层上。 该封装包含集成电路（18），该集成电路安装到附接到封装的第二表面上的散热块（22）。 集成电路耦合到位于基板的架子上的键指。 一些接合指状物（40）通过围绕搁板边缘的导电条（68）连接到内部总线上。 一些通道连接到一整套外部土地。 将焊盘（34g）分组到单个通孔减少了封装的第二表面上的通孔数量。 通孔的减小允许将额外的电容器（28）安装到封装的第二表面。