Invention Application
WO1998026301A1 INTEGRATED CIRCUIT COMPRISING A FIRST AND A SECOND CLOCK DOMAIN AND A METHOD FOR TESTING SUCH A CIRCUIT
审中-公开
包含第一和第二时钟域的集成电路和用于测试这种电路的方法
- Patent Title: INTEGRATED CIRCUIT COMPRISING A FIRST AND A SECOND CLOCK DOMAIN AND A METHOD FOR TESTING SUCH A CIRCUIT
- Patent Title (中): 包含第一和第二时钟域的集成电路和用于测试这种电路的方法
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Application No.: PCT/IB1997001346Application Date: 1997-10-27
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Publication No.: WO1998026301A1Publication Date: 1998-06-18
- Inventor: PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , MEIRLEVEDE, Johan, Corneel , BOS, Gerardus, Arnoldus, Antonius , JACOBS, Jacobus, Adrianus, Maria , LOUSBERG, Guillaume, Elisabeth, Andreas
- Applicant: PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
- Assignee: PHILIPS ELECTRONICS N.V.,PHILIPS NORDEN AB
- Current Assignee: PHILIPS ELECTRONICS N.V.,PHILIPS NORDEN AB
- Priority: NL96203534.1 19961213
- Main IPC: G01R31/3185
- IPC: G01R31/3185
Abstract:
The invention relates to an integrated circuit, comprising a number of independent clock domains. Seam circuits are provided in the interface signals paths between the clock domains in order to be able to isolate clock domains from each other during testing. Each seam circuit comprises a feedback loop having a multiplexer and a flip-flop feeding a first input of the multiplexer, a second input of the multiplexer being connected to the seam input, an output of the feedback loop being connected to the output; so that a first state of the multiplexer allows loading of a data bit in the feedback loop via the seam input, and a second state of the multiplexer freezes the data bit in the feedback loop.
Information query
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