An on-chip test circuit in an integrated circuit memory device includes a test mode terminal and a test data storage circuit having an input coupled to a data terminal of the memory device and an output coupled to a memory-cell array in the memory device. The storage circuit further includes terminals adapted to receive respective read test data and write test data signals. The storage circuit stores bits of data applied on the data terminal when the write test data signal is active. The storage circuit provides on its output the bits of stored data when the read test data signal is active. An error detection circuit includes a first input coupled to the memory-cell array and a second input coupled to the output of the storage circuit. The error detection circuit develops an active error signal on an output when the data on its input is unequal. A test control circuit is coupled to the terminals of the test data storage circuit, and to the test mode terminal. When the test mode signal is active, the test control circuit operates in a first mode to transfer data on the data terminal into the storage circuit, and operates in a second mode to transfer data from the storage circuit to the memory cells in the array. The test control circuit then operates in a third mode to access data stored in the memory cells and in the storage circuit such that the error detection circuit compares the data stored in each addressed memory cell to the data initially transferred to that memory cell.