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    SENSE AMPLIFIER FOR NON-VOLATILE SEMICONDUCTOR MEMORY
    1.
    发明申请
    SENSE AMPLIFIER FOR NON-VOLATILE SEMICONDUCTOR MEMORY 审中-公开
    用于非易失性半导体存储器的感测放大器

    公开(公告)号：WO9608822A2

    公开(公告)日：1996-03-21

    申请号：PCT/IB9500702

    申请日：1995-08-28

    Applicant: PHILIPS ELECTRONICS NV ,  PHILIPS NORDEN AB

    Inventor： TRODDEN THOMAS JOHN

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C29/38 ,  G11C29/50 ,  G11C7/06

    CPC classification number: G11C16/28 ,  G11C16/04 ,  G11C29/38 ,  G11C29/50

    Abstract: A non-volatile semiconductor memory utilizes a sense amplifier to compare the logic state of a memory cell to that of a reference cell. Loads that supply currents to the memory cell and the reference cell form a current mirror, whose amplification factor is controllably dependent on the level of the supply voltage. This configuration renders the sensitivity of the amplifier higher with a lower supply voltage than with a higher supply voltage.

    Abstract translation: 非易失性半导体存储器利用读出放大器将存储器单元的逻辑状态与参考单元的逻辑状态进行比较。 向存储器单元和参考单元提供电流的负载形成电流镜，其放大系数可控地依赖于电源电压的电平。 该配置使得放大器的灵敏度随着较低的电源电压而高于较高的电源电压。

    LINK EVALUATION FOR A MEMORY DEVICE
    2.
    发明申请
    LINK EVALUATION FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：WO2021126838A1

    公开(公告)日：2021-06-24

    申请号：PCT/US2020/065100

    申请日：2020-12-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： BALB, Markus ,  HEIN, Thomas ,  HOENIGSCHMID, Heinz

    IPC: G11C16/34 ,  G11C29/52 ,  G06F11/10 ,  G11C2207/2254 ,  G11C29/12005 ,  G11C29/38 ,  G11C29/44

    Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

    ON-CHIP CIRCUIT AND METHOD FOR TESTING MEMORY DEVICES
    5.
    发明申请
    ON-CHIP CIRCUIT AND METHOD FOR TESTING MEMORY DEVICES 审中-公开
    片内电路和测试存储器件的方法

    公开(公告)号：WO99065037A1

    公开(公告)日：1999-12-16

    申请号：PCT/US1999/013029

    申请日：1999-06-11

    IPC: G11C29/14 ,  G11C29/38 ,  G11C29/00

    CPC classification number: G11C29/14 ,  G11C29/38

    Abstract: An on-chip test circuit in an integrated circuit memory device includes a test mode terminal and a test data storage circuit having an input coupled to a data terminal of the memory device and an output coupled to a memory-cell array in the memory device. The storage circuit further includes terminals adapted to receive respective read test data and write test data signals. The storage circuit stores bits of data applied on the data terminal when the write test data signal is active. The storage circuit provides on its output the bits of stored data when the read test data signal is active. An error detection circuit includes a first input coupled to the memory-cell array and a second input coupled to the output of the storage circuit. The error detection circuit develops an active error signal on an output when the data on its input is unequal. A test control circuit is coupled to the terminals of the test data storage circuit, and to the test mode terminal. When the test mode signal is active, the test control circuit operates in a first mode to transfer data on the data terminal into the storage circuit, and operates in a second mode to transfer data from the storage circuit to the memory cells in the array. The test control circuit then operates in a third mode to access data stored in the memory cells and in the storage circuit such that the error detection circuit compares the data stored in each addressed memory cell to the data initially transferred to that memory cell.

    Abstract translation: 集成电路存储器件中的片上测试电路包括测试模式端子和测试数据存储电路，其具有耦合到存储器件的数据端的输入端和耦合到存储器件中的存储单元阵列的输出。 存储电路还包括适于接收相应的读取测试数据和写入测试数据信号的端子。 当写入测试数据信号有效时，存储电路存储应用于数据终端的数据位。 当读取测试数据信号有效时，存储电路在其输出端提供存储数据的位。 误差检测电路包括耦合到存储单元阵列的第一输入和耦合到存储电路的输出的第二输入。 当输入的数据不相等时，误差检测电路在输出端产生有效的误差信号。 测试控制电路耦合到测试数据存储电路的终端，并耦合到测试模式终端。 当测试模式信号有效时，测试控制电路以第一模式工作，将数据终端上的数据传送到存储电路中，并以第二模式工作，将数据从存储电路传输到阵列中的存储单元。 然后，测试控制电路以第三模式操作以访问存储在存储器单元和存储电路中的数据，使得误差检测电路将存储在每个寻址的存储器单元中的数据与最初传送到该存储单元的数据进行比较。

    CIRCUIT AND METHOD FOR TESTING A DIGITAL SEMI-CONDUCTOR CIRCUIT
    6.
    发明申请
    CIRCUIT AND METHOD FOR TESTING A DIGITAL SEMI-CONDUCTOR CIRCUIT 审中-公开
    测试电路及方法测试一台数字半导体电路

    公开(公告)号：WO99043004A1

    公开(公告)日：1999-08-26

    申请号：PCT/DE1998/002895

    申请日：1998-09-30

    IPC: G01R31/3183 ,  G01R31/28 ,  G11C29/10 ,  G11C29/26 ,  G11C29/34 ,  G11C29/36 ,  G11C29/38 ,  G11C29/00

    CPC classification number: G11C29/36 ,  G11C29/26 ,  G11C29/34 ,  G11C29/38

    Abstract: The present invention relates to a monolithic-integration test circuit used for checking a digital semi-conductor circuit formed on the same semi-conductor chip and comprising the following members: a plurality of elements to be checked; a checking-data model register for the intermediate storing of a checking-data model; a read- and write-circuit for writing data from the checking-data model register into the elements to be checked and for reading said data from said elements; and a comparison circuit (6) for determining whether or not a difference occurs between the written and read data in the elements to be checked. The test circuit comprises a model modification circuit (2) which can be actuated by an activation signal (3) and which modifies the checking-data model from the checking-data model register before writing the data in the elements to be checked.

    Abstract translation: 本发明涉及一种单片集成测试电路，用于测试形成于具有多个测试元件的同一半导体芯片的数字半导体电路装置，一个Prüfdatenmusterregister（1）用于测试数据模式，读出的中间存储和写入用于写入电路和读取Prüfdatenmusterregisters的数据在 并从测试元件，并通过一个比较电路（6），其被检查测试元件的内切和读出的数据的差异。 测试电路包括一个由激活信号（3）将被激活图案变化（2），该写入元件进行测试之前改变从Prüfdatenmusterregister校验数据。

    EMBEDDED MEMORY TESTING WITH STORAGE BORROWING
    9.
    发明申请
    EMBEDDED MEMORY TESTING WITH STORAGE BORROWING 审中-公开

    公开(公告)号：WO2018140133A1

    公开(公告)日：2018-08-02

    申请号：PCT/US2017/064381

    申请日：2017-12-03

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHAKRABORTY, Tapan ,  AVERBUJ, Roberto

    IPC: G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/38 ,  G11C29/44 ,  G11C29/32

    Abstract: An integrated circuit (IC) is disclosed herein for embedded memory testing with storage borrowing. In an example aspect, an integrated circuit includes a functional logic block, a memory block, and test logic. The functional logic block includes multiple storage units and is configured to store functional data in the multiple storage units during a regular operational mode. The test logic is configured to perform a test on the memory block during a testing mode. The test logic is also configured to retain memory test result data in the multiple storage units of the functional logic block during the testing mode.

    SEMICONDUCTOR MEMORY, METHOD OF TESTING SEMICONDUCTOR MEMORY, AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY
    10.
    发明申请
    SEMICONDUCTOR MEMORY, METHOD OF TESTING SEMICONDUCTOR MEMORY, AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY 审中-公开
    半导体存储器，半导体存储器的测试方法和制造半导体存储器的方法

    公开(公告)号：WO02037503A1

    公开(公告)日：2002-05-10

    申请号：PCT/JP2000/007709

    申请日：2000-11-02

    IPC: G11C29/38 ,  G11C29/00

    CPC classification number: G11C29/38 ,  G11C16/04 ,  G11C2029/0405 ,  G11C2029/1208

    Abstract: To test semiconductor memory, a printed-circuit board for burn-in or the semiconductor memory to be tested includes a comparator circuit to detect the coincidence between expected data and the data read from the semiconductor memory, and a counter circuit for counting the number of noncoincedences.

    Abstract translation: 为了测试半导体存储器，用于老化的印刷电​​路板或要测试的半导体存储器包括：比较器电路，用于检测预期数据与从半导体存储器读取的数据之间的一致性;以及计数器电路， noncoincedences。

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