A memory circuit which is provided with a memory cell array in which a plurality of memory cells are arranged at the intersections of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit which selects the address of the memory cell array. The memory circuit is further provided with an arithmetic circuit which generates address signals for testing the memory circuit, a packet decoder which designates the contents of operation of the arithmetic circuit, and an input circuit which supplies a test signal composed of a plurality of bits for designating the test operation of the packet decoder.