公开(公告)号：WO2013101006A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067674

申请日：2011-12-28

Applicant: INTEL CORPORATION ,  KOBLA, Darshan ,  ZIMMERMAN, David ,  NATARAJAN, Vimal

Inventor： KOBLA, Darshan ,  ZIMMERMAN, David ,  NATARAJAN, Vimal

IPC: G11C29/18

CPC classification number: G11C29/12 ,  G06F12/1408 ,  G11C29/18 ,  G11C2029/1806

Abstract: A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold programming values for the generic programmable address scrambler.

Abstract translation: 用于存储器电路测试引擎的通用地址扰频器。 存储器件的实施例包括具有一个或多个耦合的存储器元件的存储器堆叠，内置的自检电路，其包括用于将逻辑地址映射到存储器元件的物理地址的通用可编程地址加扰器，以及一个或 更多的寄存器用于保存通用可编程地址扰频器的编程值。

公开(公告)号：WO2020015124A1

公开(公告)日：2020-01-23

申请号：PCT/CN2018/105855

申请日：2018-09-14

Applicant: 江苏华存电子科技有限公司

Inventor： 蔡定国 ,  李庭育 ,  庄健民 ,  齐元辅

IPC: G11C29/18

Abstract: 一种侦测闪存内电性不稳定的块的方法，包括控制芯片（1）、软件程序模块（2）和闪存芯片（3），控制芯片（1）分别信号连接软件程序模块（2）和闪存芯片（3），先将测试资料写入所有块的第一页，接着将所有块擦除，再将测试资料写到所有块的所有页，最后对所有块的所有页内的资料进行比对，依照结果得到坏块表；该方法原理简单，工作效率高，可以将写的页数没有超过6个页就进行擦除而会导致块写入的资料容易出错的坏块找出来。

公开(公告)号：WO2019184959A1

公开(公告)日：2019-10-03

申请号：PCT/CN2019/079938

申请日：2019-03-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： NING, Shu-Liang

IPC: G11C29/18

Abstract: The present disclosure provides a memory device, wherein: an address latch can output a block selection control signal according to a block selection enable signal; a test mode selection unit can output a test mode selection signal according to a test mode selection instruction signal; a block selection unit outputs a block selection signal according to a mode selection signal and a block selection enable signal; when the memory enters a first test mode according to the test mode selection signal, an output buffer disables some of the input/output ports, and sequentially outputs the first input/output data and the second input/output data through un-disabled the input/output ports. The memory device according to the present disclosure can occupy less input/output ports of a test machine.

公开(公告)号：WO2022192832A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/070762

申请日：2022-02-22

Applicant: MICRON TECHNOLOGY

Inventor： WILSON, Alan, J. ,  MORGAN, Donald, M.

IPC: G11C29/44 ,  G11C29/18 ,  G06F3/06 ,  G06F12/02

Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

公开(公告)号：WO2022094047A2

公开(公告)日：2022-05-05

申请号：PCT/US2021/057008

申请日：2021-10-28

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： ALAM, Syed, M. ,  JANESKY, Jason ,  LEE, Han, Kyu ,  ALMASI, Hamid ,  SANCHEZ, Pedro ,  MASGRAS, Cristian, P. ,  RAHMAN, Iftekhar ,  IKEGAWA, Sumio ,  AGGARWAL, Sanjeev ,  HOUSSAMEDDINE, Dimitri ,  NEUMEYER, Frederick, Charles

IPC: G06F11/16 ,  G06F11/1666 ,  G11C2029/0407 ,  G11C2029/1202 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/42 ,  G11C29/4401

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

公开(公告)号：WO2021261858A1

公开(公告)日：2021-12-30

申请号：PCT/KR2021/007750

申请日：2021-06-21

Applicant: 삼성전자 주식회사

Inventor： 김제윤 ,  양승진 ,  김동우 ,  신창미 ,  김민정

IPC: G11C29/04 ,  G11C29/18 ,  G11C29/44 ,  G11C29/00 ,  G06F3/06

Abstract: 디스플레이, 반도체 메모리 모듈, 메모리 컨트롤러, 프로세서, 및 상기 프로세서에 작동적으로(operatively) 연결되는 메모리를 포함하는 전자 장치가 개시된다. 전자 장치는 지정된 주기에 기반하여 상기 반도체 메모리 모듈의 불량 메모리 셀을 검출하도록 하는 테스트 신호를 생성하고, 상기 테스트 신호를 기반으로 테스트 동작을 수행하여 상기 반도체 메모리 모듈에 포함된 메모리 셀 어레이에서 적어도 하나의 불량 메모리 셀을 검출하고, 상기 적어도 하나의 불량 메모리 셀이 검출된 경우, 상기 적어도 하나의 불량 메모리 셀과 연관된 데이터를 상기 메모리에 저장하고, 상기 메모리 컨트롤러는 상기 메모리에 저장된 상기 적어도 하나의 불량 메모리 셀과 연관된 데이터를 포함하는 리페어 신호를 생성하여 상기 반도체 메모리 모듈로 전송하도록 하는 하나 이상의 인스트럭션들(instructions)을 저장할 수 있다. 이 외에도, 명세서를 통하여 파악되는 다양한 실시예들이 가능할 수 있다.

公开(公告)号：WO2010017015A1

公开(公告)日：2010-02-11

申请号：PCT/US2009/051081

申请日：2009-07-17

Applicant: RAMBUS INC. ,  KASAMSETTY, Kishore, Ven ,  RICHARDSON, Wayne, S. ,  KNORPP, Kurt ,  WARE, Frederick, A.

Inventor： KASAMSETTY, Kishore, Ven ,  RICHARDSON, Wayne, S. ,  KNORPP, Kurt ,  WARE, Frederick, A.

IPC: G11C29/16 ,  G11C29/18

CPC classification number: G11C29/16 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/56012

Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.

Abstract translation: 描述存储器件的实施例。 该存储装置包括电连接到命令/地址（CA）链路的信号连接器和电耦合到信号连接器并且经由CA链路接收CA分组的接口电路。 给定的CA分组包括具有与存储设备中的一个或多个存储位置相对应的地址信息的地址字段。 此外，存储器件包括具有两种操作模式的控制逻辑，其中在第一操作模式期间，控制逻辑使用全场采样来解码CA分组中的地址信息，并且在第二操作模式期间，控制逻辑解码 CA分组中的部分地址信息使用子场采样。

公开(公告)号：WO00028547A1

公开(公告)日：2000-05-18

申请号：PCT/JP1998/004985

申请日：1998-11-05

IPC: G11C29/18 ,  G11C29/00 ,  G01R31/28

CPC classification number: G11C29/18 ,  G11C2029/3602

Abstract: A memory circuit which is provided with a memory cell array in which a plurality of memory cells are arranged at the intersections of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit which selects the address of the memory cell array. The memory circuit is further provided with an arithmetic circuit which generates address signals for testing the memory circuit, a packet decoder which designates the contents of operation of the arithmetic circuit, and an input circuit which supplies a test signal composed of a plurality of bits for designating the test operation of the packet decoder.

Abstract translation: 一种存储电路，其具有多个存储单元布置在多个字线和多个位线对的交点处的存储单元阵列和选择存储单元阵列的地址的外围电路。 存储器电路还设置有生成用于测试存储器电路的地址信号的运算电路，指定算术电路的操作内容的分组解码器，以及输入电路，其提供由多个比特组成的测试信号， 指定分组解码器的测试操作。

公开(公告)号：WO2023076671A1

公开(公告)日：2023-05-04

申请号：PCT/US2022/048420

申请日：2022-10-31

Applicant: SYNOPSYS, INC.

Inventor： TSHAGHARYAN, Grigor ,  HARUTYUNYAN, Gurgen ,  SHOUKOURIAN, Samvel ,  ZORIAN, Yervant

IPC: G11C29/16 ,  G11C29/52 ,  G11C29/04 ,  G11C29/10 ,  G11C29/12 ,  G11C29/18 ,  G11C29/26 ,  G11C29/34

Abstract: A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In- system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.

公开(公告)号：WO2022151707A1

公开(公告)日：2022-07-21

申请号：PCT/CN2021/109055

申请日：2021-07-28

Applicant: 长鑫存储技术有限公司

Inventor： 瞿振林 ,  张文喜

IPC: G11C29/18 ,  G11C29/56 ,  G06F11/22

Abstract: 一种内存测试方法及装置、计算机可读存储介质、电子设备，通过执行内存测试程序对内存的第一区域进行测试，第一区域为未被内存测试程序占用的区域（S110）；将第二区域的地址信息写入设备的外存储器中，第二区域为被内存测试程序占用的区域（S120）；在第一区域内存测试完成后，根据外存储器中记录的第二区域的地址信息，将内存测试程序转移到第一区域的部分区域中（S130）；执行内存测试程序对第二区域进行测试（S140）。可以实现内存的全覆盖测试。