Invention Application
WO2003020998A2 INTEGRATED CIRCUIT DEVICE AND FABRICATION USING METAL-DOPED CHALCOGENIDE MATERIALS 审中-公开
集成电路设备和使用金属聚合材料的制造

  • Patent Title: INTEGRATED CIRCUIT DEVICE AND FABRICATION USING METAL-DOPED CHALCOGENIDE MATERIALS
  • Patent Title (中): 集成电路设备和使用金属聚合材料的制造
  • Application No.: PCT/US2002/027526
    Application Date: 2002-08-30
  • Publication No.: WO2003020998A2
    Publication Date: 2003-03-13
  • Inventor: LI, JiutaoMCTEER, Allen
  • Applicant: MICRON TECHNOLOGY, INC.
  • Applicant Address: 8000 South Federal Way, P.O. Box 6, Boise, ID 83707-0006 US
  • Assignee: MICRON TECHNOLOGY, INC.
  • Current Assignee: MICRON TECHNOLOGY, INC.
  • Current Assignee Address: 8000 South Federal Way, P.O. Box 6, Boise, ID 83707-0006 US
  • Agency: THRONSON, Mark, J.
  • Priority: US09/943,426 20010830
  • Main IPC: C23C14/18
  • IPC: C23C14/18
INTEGRATED CIRCUIT DEVICE AND FABRICATION USING METAL-DOPED CHALCOGENIDE MATERIALS
Abstract:
Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer (in situ. )In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer (in situ )with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.a
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