公开(公告)号：WO2004020683A2

公开(公告)日：2004-03-11

申请号：PCT/US2003/026814

申请日：2003-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LI, Jiutao ,  HAMPTON, Keith ,  MCTEER, Allen

IPC: C23C

CPC classification number: H01L21/02631 ,  C23C14/0021 ,  C23C14/0623 ,  C23C14/3407 ,  C23C14/3492 ,  C23C14/548 ,  H01L21/02266 ,  Y10S428/938 ,  Y10T428/12896

Abstract: A method of sputter depositing silver-selenide and controlling the stoichiometry, nodular defect formations, and crystalline structure of a sputter deposited silver-selenide film. The method includes depositing silver-selenide using a sputter deposition process at a pressure of about 0.3 mTorr to about 10 mTorr. In accordance with one aspect of the invention, an RF sputter deposition process may be used preferably at pressures of about 2 mTorr to about 3 mTorr. In accordance with another aspect of the invention, a pulse DC sputter deposition process may be used preferably at pressures of about 4 mTorr to about 5 mTorr. In accordance with another aspect of the invention, silver-selenide films containing both alpha and beta silver-selenide,may be sputter deposited under pressures of about 10 mTorr and sputter powers of less than about 250W.

Abstract translation: 溅射沉积银硒并控制溅射沉积的银硒膜的化学计量，结节缺陷形成和晶体结构的方法。 该方法包括使用溅射沉积工艺在约0.3mTorr至约10mTorr的压力下沉积硒化银。 根据本发明的一个方面，RF溅射沉积工艺可以优选地在约2mTorr至约3mTorr的压力下使用。 根据本发明的另一方面，脉冲DC溅射沉积工艺可优选地在约4mTorr至约5mTorr的压力下使用。 根据本发明的另一方面，含有α和β硒化银的硒化银膜可以在约10mTorr的压力和小于约250W的溅射功率下溅射沉积。

公开(公告)号：WO2005101539A1

公开(公告)日：2005-10-27

申请号：PCT/US2005/009957

申请日：2005-03-24

Applicant: MICRON TECHNOLOGY, INC. ,  CAMPBELL, Kristy, A. ,  LI, Jiutao ,  MCTEER, Allen ,  MOORE, John, T.

Inventor： CAMPBELL, Kristy, A. ,  LI, Jiutao ,  MCTEER, Allen ,  MOORE, John, T.

IPC: H01L45/00

CPC classification number: H01L45/085 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/1616 ,  H01L45/1625

Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to the invention, a resistance variable memory element is provided having at least one metal containing layer (18), preferably a silver-selenide layer, in between two chalcogenide glass layers (17, 20), preferably having Ge x Se 100-x composition, and top and bottom electrodes (14, 22). A metal layer (50), preferably a silver layer, is provided above at least the second chalcogenide glass layer (20) and a conductive adhesion layer (30) is disposed above said silver layer. According to another embodiment of the invention, a resistance variable memory element is provided having a first chalcogenide glass layer (17), a silver layer (40’) over said first chalcogenide glass layer, a silver selenide layer (18) over said silver layer, a second chalcogenide glass layer (20) over said silver selenide layer, and optionally a second silver layer over said second chalcogenide glass layer.

Abstract translation: 本发明涉及用于提供具有改进的数据保持和切换特性的电阻可变存储元件的方法和装置。 根据本发明，提供一种电阻可变存储元件，其具有至少一个金属含有层（18），优选为银硒化物层，位于两个优选具有GexSe100-x组成的硫族化物玻璃层（17,20）之间，以及 顶部和底部电极（14,22）。 至少在第二硫族化物玻璃层（20）的上方设置金属层（50），优选为银层，在所述银层的上方配置有导电性粘接层（30）。 根据本发明的另一个实施例，提供一种电阻可变存储元件，其具有第一硫族化物玻璃层（17），在所述第一硫族化物玻璃层上方的银层（40'），所述银层上方的银硒层（18） ，在所述硒化银层上方的第二硫族化物玻璃层（20），以及任选地在所述第二硫族化物玻璃层上方的第二银层。

公开(公告)号：WO2007103471A2

公开(公告)日：2007-09-13

申请号：PCT/US2007/005886

申请日：2007-03-07

Applicant: MICRON TECHNOLOGY, INC. ,  MCTEER, Allen

Inventor： MCTEER, Allen

IPC: C23C14/00 ,  C23C14/06

CPC classification number: C23C14/0042 ,  C23C14/0057 ,  C23C14/0094 ,  C23C14/0652 ,  C23C14/3485

Abstract: There is provided a system and method for sputtering a tensile silicon nitride film. More specifically, in one embodiment, there is provided a method comprising introducing nitrogen gas into a process chamber, wherein the process chamber includes a target comprising silicon, placing the process chamber into a transition region between a metallic region and a poisoned region, and applying a voltage to the target.

Abstract translation: 提供了用于溅射拉伸氮化硅膜的系统和方法。 更具体地，在一个实施例中，提供了一种方法，该方法包括将氮气引入到处理室中，其中该处理室包括含硅的目标，将处理室放置在金属区域和中毒区域之间的过渡区域中， 给目标一个电压。

公开(公告)号：WO2003020998A3

公开(公告)日：2003-03-13

申请号：PCT/US2002/027526

申请日：2002-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LI, Jiutao ,  MCTEER, Allen

IPC: C23C14/18

Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer (in situ. )In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer (in situ )with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.a

公开(公告)号：WO2003020998A2

公开(公告)日：2003-03-13

申请号：PCT/US2002/027526

申请日：2002-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LI, Jiutao ,  MCTEER, Allen

IPC: C23C14/18

CPC classification number: C23C14/5846 ,  C23C14/0623 ,  C23C14/544 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/1658

Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer (in situ. )In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer (in situ )with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.a

Abstract translation: 形成掺杂金属的硫族化物层的方法和包含这种掺杂的硫族化物层的器件包括使用等离子体来诱导金属与金属沉积同时扩散到硫族化物层中。 等离子体包含至少一种低原子量的惰性气体，例如氖或氦。 等离子体具有足以溅射金属靶的溅射产率和其发射光谱的UV分量足以引起溅射金属扩散到硫族化物层中。 使用这种方法，可以在掺杂的硫族化物层（原位）上形成导电层。在诸如非挥发性硫族化物存储器件的集成电路器件中，与金属沉积和形成导电层同时掺杂硫族化物层（ 原位）随着硫族化物层的掺杂而减少了由于将器件基板从工具移动到工具而导致的污染问题和物理损坏，从而有助于提高器件的可靠性。