A method for carrying out computations of modular exponentiation (M E mod N) by hardware involving Montgomery multiplication operations utilizing a non-reduced and extended Montgomery multiplication between a first (A) and a second (B) integer values, in which the number of iterations required is greater than the number of bits n of an odd modulus value N, and a pre-calculated auxiliary operand value M'=M*2 s mod N. The method comprises carrying out non-reduced and extended Montgomery multiplication (NRMM (s) ), by utilizing a first and a second multiplication units capable of storing the result of said multiplication. A pre-calculated auxiliary operand value M' is stored in the second multiplication unit and in a storage device. The following step are then performed: non-reduced and extended Montgomery multiplication is performed by the second multiplication unit, of its content by itself (NFMM (s) (M',M')), thereby obtaining non-reduced and extended Montgomery squaring of the content of said second multiplication unit; sequentially scanning the exponent bits E i (i=0,1, ) starting from its LSB, checking the state of each bit, and if the bit state is "1" and it is the first occurrence of exponent bit of state "1", the content of the second multiplication unit is stored in the first multiplication unit, otherwise, a non-reduced and extended Montgomery multiplication is performed by the first multiplication unit, of its content by the value stored in the storage device; storing the result of in the storage device; and repeating steps the above steps until all of the exponent bits are scanned. The modular exponentiation result is obtained by performing non-reduced and extend Montgomery multiplication, by the first multiplication unit, of its content, by 1.