公开(公告)号：WO2003023601A3

公开(公告)日：2003-03-20

申请号：PCT/IL2002/000317

申请日：2002-04-22

Applicant: DISCRETIX TECHNOLOGIES LTD ,  GUERON, Shay ,  HADAD, Isaac

Inventor： GUERON, Shay ,  HADAD, Isaac

IPC: G06F7/72

Abstract: A method for carrying out computations of modular exponentiation (M E mod N) by hardware involving Montgomery multiplication operations utilizing a non-reduced and extended Montgomery multiplication between a first (A) and a second (B) integer values, in which the number of iterations required is greater than the number of bits n of an odd modulus value N, and a pre-calculated auxiliary operand value M'=M*2 s mod N. The method comprises carrying out non-reduced and extended Montgomery multiplication (NRMM (s) ), by utilizing a first and a second multiplication units capable of storing the result of said multiplication. A pre-calculated auxiliary operand value M' is stored in the second multiplication unit and in a storage device. The following step are then performed: non-reduced and extended Montgomery multiplication is performed by the second multiplication unit, of its content by itself (NFMM (s) (M',M')), thereby obtaining non-reduced and extended Montgomery squaring of the content of said second multiplication unit; sequentially scanning the exponent bits E i (i=0,1, ) starting from its LSB, checking the state of each bit, and if the bit state is "1" and it is the first occurrence of exponent bit of state "1", the content of the second multiplication unit is stored in the first multiplication unit, otherwise, a non-reduced and extended Montgomery multiplication is performed by the first multiplication unit, of its content by the value stored in the storage device; storing the result of in the storage device; and repeating steps the above steps until all of the exponent bits are scanned. The modular exponentiation result is obtained by performing non-reduced and extend Montgomery multiplication, by the first multiplication unit, of its content, by 1.

公开(公告)号：WO2003001362A2

公开(公告)日：2003-01-03

申请号：PCT/IL2002/000318

申请日：2002-04-22

Applicant: DISCRETIX TECHNOLOGIES LTD. ,  GUERON, Shay ,  HADAD, Isaac

Inventor： GUERON, Shay ,  HADAD, Isaac

IPC: G06F7/00

CPC classification number: G06F7/728

Abstract: A method for carrying out modular arithmetic computations involving multiplication operations by utilizing a non-reduced and extended Montgomery multiplication between a first A and a second B integer values, in which the number of iterations required is greater than the number of bits n of an odd modulo value N. The method comprises storing n+2 bit values in an accumulating device (S) capable of, of adding n+2-bit values (X) to it content, and of dividing its content by 2. Whenever desired, the content of the accumulating device is set to zero value. At least s(>n+1) iterations of the following steps are performed, while in each iteration choosing one bit, in sequence, from the value of said first integer value A, starting from its least significant bit: adding to the content of the accumulating device S the product of the selected bit and said second integer value B; adding to the resulting content the product of its current least significant bit and N; dividing the result by 2; and obtaining a non-reduced and extended Montgomery multiplication result by repeating these steps s-1 additional times while in each time using the previous result (S).

Abstract translation: 一种通过利用第一个A和一个第二个B整数值之间的非还原和扩展的蒙哥马利乘法执行涉及乘法运算的模数运算的方法，其中所需的迭代次数大于奇数的位数n 该方法包括将n + 2位值存储在能够向其内容添加n + 2位值（X）并将其内容除以2的累加装置（S）中。当需要时， 累积装置的内容被设定为零值。 执行以下步骤的至少s（> n + 1）个迭代，而在每次迭代中，从所述第一整数值A的值中选择一个位，从其最低有效位开始：添加到 累积装置S是所选位和所述第二整数值B的乘积; 将所得到的内容加上其当前最低有效位和N的乘积; 将结果除以2; 并且通过在每次使用先前结果（S）的情况下重复这些步骤s-1，获得未缩减和扩展的蒙哥马利倍增结果。

公开(公告)号：WO2003023601A2

公开(公告)日：2003-03-20

申请号：PCT/IL2002/000317

申请日：2002-04-22

Applicant: DISCRETIX TECHNOLOGIES LTD ,  GUERON, Shay ,  HADAD, Isaac

Inventor： GUERON, Shay ,  HADAD, Isaac

IPC: G06F7/00

CPC classification number: G06F7/728

Abstract: A method for carrying out computations of modular exponentiation (M E mod N) by hardware involving Montgomery multiplication operations utilizing a non-reduced and extended Montgomery multiplication between a first (A) and a second (B) integer values, in which the number of iterations required is greater than the number of bits n of an odd modulus value N, and a pre-calculated auxiliary operand value M'=M*2 s mod N. The method comprises carrying out non-reduced and extended Montgomery multiplication (NRMM (s) ), by utilizing a first and a second multiplication units capable of storing the result of said multiplication. A pre-calculated auxiliary operand value M' is stored in the second multiplication unit and in a storage device. The following step are then performed: non-reduced and extended Montgomery multiplication is performed by the second multiplication unit, of its content by itself (NFMM (s) (M',M')), thereby obtaining non-reduced and extended Montgomery squaring of the content of said second multiplication unit; sequentially scanning the exponent bits E i (i=0,1, ) starting from its LSB, checking the state of each bit, and if the bit state is "1" and it is the first occurrence of exponent bit of state "1", the content of the second multiplication unit is stored in the first multiplication unit, otherwise, a non-reduced and extended Montgomery multiplication is performed by the first multiplication unit, of its content by the value stored in the storage device; storing the result of in the storage device; and repeating steps the above steps until all of the exponent bits are scanned. The modular exponentiation result is obtained by performing non-reduced and extend Montgomery multiplication, by the first multiplication unit, of its content, by 1.

Abstract translation: 一种用于通过使用在第一（A）和第二（B）整数值之间的非缩减和扩展的蒙哥马利乘法进行蒙哥马利乘法运算的硬件来执行模幂运算（M？mod mod N）的方法，其中 所需的迭代次数大于奇数模数值N的位数n，以及预先计算的辅助操作数值M'= M * 2 mod N.该方法包括执行非还原和扩展的蒙哥马利 通过利用能够存储所述乘法的结果的第一和第二乘法单元来乘法（NRMM <（s）>）。 预先计算的辅助操作数值M'存储在第二乘法单元和存储装置中。 然后执行以下步骤：非缩减和扩展的蒙哥马利乘法由其内容本身的第二乘法单元执行（NFMM <（s>>（M'，M'）），从而获得未缩减和扩展 所述第二乘法单元的内容的蒙哥马利平方; 顺序扫描从其LSB开始的指数位Ei（i = 0,1），检查每个位的状态，如果位状态为“1”，并且它是状态“1”的指数位的第一次出现， 第二乘法单元的内容被存储在第一乘法单元中，否则，由存储在存储设备中的值的内容由其第一乘法单元执行非缩减扩展的蒙哥马利乘法; 存储在存储装置中的结果; 并重复上述步骤，直到扫描所有指数位。 通过执行非缩减并通过第一乘法单元将其内容的Montgomery乘法乘以1获得模幂运算结果。

公开(公告)号：WO2003001362A3

公开(公告)日：2003-01-03

申请号：PCT/IL2002/000318

申请日：2002-04-22

Applicant: DISCRETIX TECHNOLOGIES LTD. ,  GUERON, Shay ,  HADAD, Isaac

Inventor： GUERON, Shay ,  HADAD, Isaac

IPC: G06F7/72

Abstract: A method for carrying out modular arithmetic computations involving multiplication operations by utilizing a non-reduced and extended Montgomery multiplication between a first A and a second B integer values, in which the number of iterations required is greater than the number of bits n of an odd modulo value N. The method comprises storing n+2 bit values in an accumulating device (S) capable of, of adding n+2-bit values (X) to it content, and of dividing its content by 2. Whenever desired, the content of the accumulating device is set to zero value. At least s(>n+1) iterations of the following steps are performed, while in each iteration choosing one bit, in sequence, from the value of said first integer value A, starting from its least significant bit: adding to the content of the accumulating device S the product of the selected bit and said second integer value B; adding to the resulting content the product of its current least significant bit and N; dividing the result by 2; and obtaining a non-reduced and extended Montgomery multiplication result by repeating these steps s-1 additional times while in each time using the previous result (S).

公开(公告)号：WO2004063842A2

公开(公告)日：2004-07-29

申请号：PCT/IL2004/000050

申请日：2004-01-18

Applicant: DISCRETIX TECHNOLOGIES LTD. ,  HADAD, Isaac

Inventor： HADAD, Isaac

IPC: G06F

CPC classification number: H04L9/0643 ,  H04L2209/12

Abstract: Embodiments of the invention provide a hash function module for carrying out hash function computations of at least two different hash function algorithms. According to some exemplary embodiments of the invention, the hash function module includes a read -write memory, an accumulating device, an adder, exclusive-or circuitry, one or more cyclic bit rotation devices, two arbitration devices, at least three data registers, one or more logical function circuitries, and a control circuit.

Abstract translation: 本发明的实施例提供了一种用于执行至少两个不同散列函数算法的散列函数计算的散列函数模块。 根据本发明的一些示例性实施例，散列函数模块包括读写存储器，累加器件，加法器，异或电路，一个或多个循环位旋转器件，两个仲裁器件，至少三个数据寄存器， 一个或多个逻辑功能电路，以及控制电路。

公开(公告)号：WO2012014196A1

公开(公告)日：2012-02-02

申请号：PCT/IL2011/000595

申请日：2011-07-24

Applicant: WALLETEX MICROELECTRONICS LTD. ,  HADAD, Isaac ,  YAARI, Doron ,  GAM, Zvi ,  DAHAN, Abraham

Inventor： HADAD, Isaac ,  YAARI, Doron ,  GAM, Zvi ,  DAHAN, Abraham

IPC: G06F13/12

CPC classification number: G06F3/0661 ,  G06F3/0607 ,  G06F3/0679

Abstract: A method for transferring non-standard commands to a device having storage and processing capabilities and that is capable of being linked to a host computer, said method comprising creating a designated file in said device, analyzing any standard write command attempting to access said designated file to determine whether it incorporates a non-standard command, and executing said non-standard command if incorporated in said standard write command. A device for carrying out said method is also disclosed.

Abstract translation: 一种用于将非标准命令传送到具有存储和处理能力并且能够被链接到主计算机的设备的方法，所述方法包括在所述设备中创建指定的文件，分析尝试访问所述指定文件的任何标准写命令 以确定其是否包含非标准命令，以及如果并入所述标准写入命令中则执行所述非标准命令。 还公开了一种用于执行所述方法的装置。

公开(公告)号：WO2010026591A1

公开(公告)日：2010-03-11

申请号：PCT/IL2009/000866

申请日：2009-09-06

Applicant: WALLETEX MICROELECTRONICS LTD. ,  HADAD, Isaac ,  GAM, Zvi ,  DAHAN, Abraham

Inventor： HADAD, Isaac ,  GAM, Zvi ,  DAHAN, Abraham

IPC: G06F21/20 ,  H04L9/32 ,  H04L29/06

CPC classification number: H04L63/0853 ,  G06F21/34 ,  G06F21/36 ,  G06F2221/2103 ,  G06F2221/2133 ,  G06Q20/388 ,  H04L63/1441 ,  H04L63/166

Abstract: The present invention provides a system, method and device, for carrying out secure electronic communication over a computer network via a computer susceptible of being virus infected or eavesdropped by means of a personal apparatus comprising processing means, one or more memory devices, one or more interfacing means suitable for exchanging information with the insecure computer, and a communication software having cryptographic capabilities stored in the one or more memory means, wherein the personal apparatus is adapted to establish a secure channel with a remote computer over the computer network, by means of the insecure computer machine.

Abstract translation: 本发明提供一种系统，方法和装置，用于经由计算机网络执行安全的电子通信，所述计算机易受病毒感染或通过个人设备窃听，所述个人设备包括处理装置，一个或多个存储设备，一个或多个 适于与不安全计算机交换信息的接口装置，以及具有存储在所述一个或多个存储器装置中的加密能力的通信软件，其中所述个人装置适于通过所述计算机网络与远程计算机建立安全通道，借助于 不安全的电脑机器。

公开(公告)号：WO2010052722A1

公开(公告)日：2010-05-14

申请号：PCT/IL2009/001056

申请日：2009-11-10

Applicant: WALLETEX MICROELECTRONICS LTD. ,  HADAD, Isaac ,  GAM, Zvi ,  DAHAN, Abraham

Inventor： HADAD, Isaac ,  GAM, Zvi ,  DAHAN, Abraham

IPC: G06F21/02

CPC classification number: G06F21/79

Abstract: The present invention provides a secure handheld portable storage device comprising a nonvolatile memory, data communication connectivity means, a secure processor operated with a secure operating system, and interfacing means for interfacing between the secure processor and a data processing system and the nonvolatile memory, wherein the secure processor comprises a cpu, a secure memory, and optionally PKI, and/or encryption/decryption means.

Abstract translation: 本发明提供了一种安全的手持便携式存储设备，其包括非易失性存储器，数据通信连接装置，利用安全操作系统操作的安全处理器以及用于在安全处理器与数据处理系统和非易失性存储器之间进行接口的接口装置，其中 安全处理器包括cpu，安全存储器和可选地PKI和/或加密/解密装置。