Invention Application
- Patent Title: SUBLITHOGRAPHIC NANOSCALE MEMORY ARCHITECTURE
- Patent Title (中): 分层纳米存储器架构
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Application No.: PCT/US0323199Application Date: 2003-07-24
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Publication No.: WO2004034467A3Publication Date: 2004-08-26
- Inventor: DEHON ANDRE , LIEBER CHARLES M , LINCOLN PATRICK D , SAVAGE JOHN
- Applicant: DEHON ANDRE , LIEBER CHARLES M , LINCOLN PATRICK D , SAVAGE JOHN
- Assignee: DEHON ANDRE,LIEBER CHARLES M,LINCOLN PATRICK D,SAVAGE JOHN
- Current Assignee: DEHON ANDRE,LIEBER CHARLES M,LINCOLN PATRICK D,SAVAGE JOHN
- Priority: US39894302 2002-07-25; US40039402 2002-08-01; US41517602 2002-09-30; US42901002 2002-11-25; US44199503 2003-01-23; US46535703 2003-04-25; US46738803 2003-05-02
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C8/10 ; G11C13/02 ; H01L21/3205 ; H01L23/52 ; H01L23/522 ; H01L27/10 ; H01L29/06 ; H01L49/00
Abstract:
A memory array comprising nanoscale wires (61-72) is disclosed. The nanoscale wiresare addressed by means of controllable regions (80, 82) axially and/or radiallydistributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires andmicroscale wires. In a two-dimensional emobdiment, memory locations (75) aredefined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing pointsbetween nanoscale wires located in different vertical layers.
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