Invention Application
- Patent Title: LOW TEMPERATURE PROCESS FOR TFT FABRICATION
- Patent Title (中): TFT制造的低温工艺
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Application No.: PCT/US2004017236Application Date: 2004-06-01
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Publication No.: WO2004112104A3Publication Date: 2005-03-17
- Inventor: HSIAO MARK , YIM DONG-KIL , TAKEHARA TAKAKO , SHANG QUANYUAN , HARSHBARGER WILLIAM R , KIM WOONG-KWON , YUN DUK-CHUL , CHANG YOU-GYUNG
- Applicant: APPLIED MATERIALS INC , HSIAO MARK , YIM DONG-KIL , TAKEHARA TAKAKO , SHANG QUANYUAN , HARSHBARGER WILLIAM R , KIM WOONG-KWON , YUN DUK-CHUL , CHANG YOU-GYUNG
- Assignee: APPLIED MATERIALS INC,HSIAO MARK,YIM DONG-KIL,TAKEHARA TAKAKO,SHANG QUANYUAN,HARSHBARGER WILLIAM R,KIM WOONG-KWON,YUN DUK-CHUL,CHANG YOU-GYUNG
- Current Assignee: APPLIED MATERIALS INC,HSIAO MARK,YIM DONG-KIL,TAKEHARA TAKAKO,SHANG QUANYUAN,HARSHBARGER WILLIAM R,KIM WOONG-KWON,YUN DUK-CHUL,CHANG YOU-GYUNG
- Priority: US45333303 2003-06-02
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/49 ; H01L29/786
Abstract:
Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300 °C or less.
Information query
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