ARRAY OF NANOSCOPIC MOSFET TRANSISTORS AND FABRICATION METHODS

Invention Application

WO2005010981A2 ARRAY OF NANOSCOPIC MOSFET TRANSISTORS AND FABRICATION METHODS 审中-公开

Title translation: 纳米MOSFET晶体管阵列和制造方法

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Patent Title: ARRAY OF NANOSCOPIC MOSFET TRANSISTORS AND FABRICATION METHODS
Patent Title (中): 纳米MOSFET晶体管阵列和制造方法
Application No.: PCT/US2004/020675

Application Date: 2004-06-25
Publication No.: WO2005010981A2

Publication Date: 2005-02-03
Inventor: GHOZEIL, Adam, L. , STASIAK, James , PETERS, Kevin, F. , KAWAMOTO, Galen, H.
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , GHOZEIL, Adam, L. , STASIAK, James , PETERS, Kevin, F. , KAWAMOTO, Galen, H.
Applicant Address: Hewlett-Packard Company, Intellectual Property Administration, 20555 S.H. 249, Houston, Texas 77070 US
Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.,GHOZEIL, Adam, L.,STASIAK, James,PETERS, Kevin, F.,KAWAMOTO, Galen, H.
Current Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.,GHOZEIL, Adam, L.,STASIAK, James,PETERS, Kevin, F.,KAWAMOTO, Galen, H.
Current Assignee Address: Hewlett-Packard Company, Intellectual Property Administration, 20555 S.H. 249, Houston, Texas 77070 US
Agency: WADE, Matthew, L.
Priority: US10/620,858 20030715
Main IPC: H01L21/8234
IPC: H01L21/8234

ARRAY OF NANOSCOPIC MOSFET TRANSISTORS AND FABRICATION METHODS

Abstract:

A nanoscopic transistor (20) is made by forming an oxide layer on a semiconductor substrate (S10, S20), applying resist (S30), patterning the resist using imprint lithography to form a pattern aligned along a first direction (S40), applying a first ion-masking material over the pattern (S50), selectively lifting it off to leave a first ion mask to form a gate (S60), forming doped regions by implanting a suitable dopant (S70), applying another layer of resist (S90) and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction (S100), applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern (S120), and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask (S130). The method may be used to make an array (10 or 15) of nanoscopic transistors (20).

Abstract(Chinese):

通过在半导体衬底上形成氧化层（S10，S20），涂敷抗蚀剂（S30），使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案（S40），制成纳米级晶体管（20）（S50），选择性地将其离开离开第一离子掩模以形成栅极（S60），通过注入合适的掺杂剂形成掺杂区域（S70），施加另一层抗蚀剂（S90）以及使用压印光刻对所述第二抗蚀剂层进行构图以形成沿着第二方向对准的第二图案（S100），在所述第二图案上施加第二离子掩模材料，选择性地将其提起以离开由所述第二图案限定的第二离子掩模（S120），并且通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域（S130）。该方法可用于制造纳米级晶体管（20）的阵列（10或15）。

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺