Invention Application
WO2005045901A8 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES
审中-公开
用于形成用于CMOS器件的应变Si的方法和结构
- Patent Title: METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES
- Patent Title (中): 用于形成用于CMOS器件的应变Si的方法和结构
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Application No.: PCT/US2004037049Application Date: 2004-11-05
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Publication No.: WO2005045901A8Publication Date: 2006-02-02
- Inventor: STEEGEN AN L , YANG HAINING S , ZHANG YING
- Applicant: IBM , STEEGEN AN L , YANG HAINING S , ZHANG YING
- Assignee: IBM,STEEGEN AN L,YANG HAINING S,ZHANG YING
- Current Assignee: IBM,STEEGEN AN L,YANG HAINING S,ZHANG YING
- Priority: US60590603 2003-11-05
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/265 ; H01L21/336 ; H01L21/762 ; H01L21/8238 ; H01L29/10 ; H01L29/78 ; H01L
Abstract:
A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.
Public/Granted literature
- WO2005045901A3 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES Public/Granted day:2006-08-17
Information query
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