公开(公告)号：WO2023064015A1

公开(公告)日：2023-04-20

申请号：PCT/US2022/036083

申请日：2022-07-05

Applicant: APPLIED MATERIALS, INC.

Inventor： LIU, Chengyu ,  XIONG, Ruitong ,  XIE, Bo ,  TANG, Xianmin ,  LIU, Yijun ,  XIA, Li-Qun

IPC: H01L21/762 ,  H01L21/02 ,  C23C14/16 ,  C23C14/04 ,  C23C14/34

Abstract: A method for dielectric filling of a feature on a substrate yields a seamless dielectric fill with high-k for narrow features. In some embodiments, the method may include depositing a metal material into the feature to fill the feature from a bottom of the feature wherein the feature has an opening ranging from less than 20nm to approximately 150nm at an upper surface of the substrate and wherein depositing the metal material is performed using a high ionization physical vapor deposition (PVD) process to form a seamless metal gap fill and treating the seamless metal gap fill by oxidizing/nitridizing the metal material of the seamless metal gap fill with an oxidation/nitridation process to form dielectric material wherein the seamless metal gap fill is converted into a seamless dielectric gap fill with high-k dielectric material.

公开(公告)号：WO2023030896A1

公开(公告)日：2023-03-09

申请号：PCT/EP2022/073007

申请日：2022-08-17

Applicant: SOITEC

Inventor： CHARLES-ALFRED, Cédric ,  BEN MOHAMED, Nadia

IPC: H01L21/18 ,  H01L21/762 ,  H01L41/312 ,  H01L21/02

Abstract: L'invention concerne un procédé de transfert d'une couche utile (15) sur un substrat support (20), le procédé comprenant : a) la fourniture d'un substrat donneur (10) qui comprend une couche donneuse (12); b) la formation d'une zone de fragilisation (14), par implantation d'espèces dans la couche donneuse (12), qui délimite avec cette dernière une couche utile (15); c) l'assemblage du substrat support (20) avec le substrat donneur (10); d) un traitement thermique qui comprend une première et une deuxième phase, la première phase, d'une première durée, comprend une élévation à une première température, et est adaptée pour permettre une maturation de défauts, et prévenir l'initiation d'une fracture dans ladite zone (14), la deuxième phase, d'une deuxième durée, comprend un palier à une deuxième température, inférieure à la première température, et est adaptée pour initier une fracture le long de la zone de fragilisation.

公开(公告)号：WO2023028853A1

公开(公告)日：2023-03-09

申请号：PCT/CN2021/115743

申请日：2021-08-31

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： LIU, Wei ,  ZHU, Hongbin ,  HUA, Zi Qun ,  JIANG, Ning ,  HUA, Wenyu

IPC: H01L27/11578 ,  H01L27/11529 ,  H01L21/762 ,  H01L21/768

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the first bonding interface.

公开(公告)号：WO2023028825A1

公开(公告)日：2023-03-09

申请号：PCT/CN2021/115613

申请日：2021-08-31

Applicant: 长江存储科技有限责任公司

Inventor： 侯会丹 ,  姚兰 ,  石艳伟

IPC: H01L21/762 ,  H01L27/146

Abstract: 本发明公开了一种半导体器件及其制备方法，先对第一器件区的衬底进行刻蚀形成至少一个第一沟槽，然后对第一器件区和第二器件区的衬底进行刻蚀，以在第一沟槽的位置对应形成第一隔离槽和在第二器件区形成第二隔离槽。其中，第一隔离槽的深度大于第二隔离槽的深度。

公开(公告)号：WO2023019523A1

公开(公告)日：2023-02-23

申请号：PCT/CN2021/113595

申请日：2021-08-19

Applicant: 长鑫存储技术有限公司

Inventor： 卢经文

IPC: H01L21/762 ,  H01L21/768

Abstract: 本公开公开了一种半导体器件、电子设备及制备方法，通过在半导体衬底上先形成字线沟槽，之后在字线沟槽中形成字线结构，之后再形成有源区。这样可以使字线沟槽穿过半导体衬底，而不需要使字线沟槽穿过其他材料。由于半导体衬底的材料均一，从而不存在刻蚀选择比的问题，进而使形成的字线沟槽的底面可以平整。在字线沟槽中形成字线结构时，可以使字线结构与半导体衬底直接接触，而不需要使字线结构与其他材料进行接触，从而可以使字线结构的底面可以平整，进而提高半导体器件的性能和可靠性。

公开(公告)号：WO2023009311A1

公开(公告)日：2023-02-02

申请号：PCT/US2022/036882

申请日：2022-07-13

Applicant: APPLIED MATERIALS, INC.

Inventor： LEE, Jung Chan ,  PARK, Mun Kyu ,  LEE, Jun ,  LEE, Euhngi ,  SHIM, Kyu-Ha ,  MITTAL, Deven Matthew Raj ,  JO, Sungho ,  MILLER, Timothy ,  LIANG, Jingmei ,  JHA, Praket Prakash ,  KAMATH, Sanjay G.

IPC: H01L21/02 ,  H01L21/762

Abstract: Embodiments of the present disclosure generally relate to methods for gap fill deposition and film densification on microelectronic devices. The method includes forming an oxide layer containing silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, and exposing the oxide layer to a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias. The method also includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer. The second plasma treatment includes generating a second plasma by top and side RF sources and directing the second plasma to the treated oxide layer without a bias. The densified oxide layer has a final WER of less than one-half of the initial WER.

公开(公告)号：WO2023287959A2

公开(公告)日：2023-01-19

申请号：PCT/US2022/037082

申请日：2022-07-14

Applicant: PSIQUANTUM, CORP.

Inventor： LIANG, Yong ,  KAMINENI, Vimal Kumar ,  CHANG, Chia-Ming ,  MCMAHON, James

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/786 ,  A23L33/00 ,  H01L21/02186 ,  H01L23/562 ,  H01L27/1203

Abstract: A method includes depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.

公开(公告)号：WO2022257313A1

公开(公告)日：2022-12-15

申请号：PCT/CN2021/123711

申请日：2021-10-14

Applicant: 武汉新芯集成电路制造有限公司

Inventor： 杨帆 ,  胡胜 ,  盛备备

IPC: H01L29/06 ,  H01L21/762

Abstract: 本发明提供了一种半导体器件及其制造方法，所述半导体器件包括：第一晶圆；沟槽隔离环，形成于所述第一晶圆中，所述沟槽隔离环包括第一金属层；第一绝缘介质层，形成于所述第一晶圆的表面，所述第一绝缘介质层中形成有至少一个第一通孔和至少一个第二通孔，所述第一通孔暴露出所述第一金属层的表面，所述第二通孔暴露出所述第一晶圆的表面；阻挡层，至少形成于所述第二通孔暴露出的所述第一晶圆的表面；以及，第二金属层，形成于所述第一绝缘介质层上，且所述第二金属层填充所述第一通孔和所述第二通孔。本发明的技术方案能够避免导致接触电阻增大以及铝尖峰等问题，提高了半导体器件的制造工艺的稳定性以及提高了半导体器件的性能。

公开(公告)号：WO2022212327A1

公开(公告)日：2022-10-06

申请号：PCT/US2022/022285

申请日：2022-03-29

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： PALACIOS, Tomas ,  ZUBAIR, Ahmad ,  NIROULA, John

IPC: H01L29/70 ,  H01L29/739 ,  H01L21/762 ,  H01L29/772 ,  H01L29/778 ,  H01L29/861

Abstract: A semiconductor device having an electric field management layer. The electric field management layer comprises a material with a relatively high dielectric constant that minimizes the risk of an electric field within the semiconductor device breaking down and damaging the semiconductor device.

公开(公告)号：WO2022195226A1

公开(公告)日：2022-09-22

申请号：PCT/FR2022/050479

申请日：2022-03-17

Applicant: SOITEC

Inventor： RADU, Ionut ,  BESNARD, Guillaume ,  CRISTOLOVEANU, Sorin

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

Abstract: L'invention concerne un transistor NC-FET comportant un substrat de type semi-conducteur sur isolant pour un transistor à effet de champ, comprenant successivement, de sa base vers sa surface : o un substrat support (1) semiconducteur, o une unique couche (2) ferroélectrique, agencée en contact direct avec le substrat support (1), adaptée pour être polarisée de sorte à former une capacité négative, et o une couche active (3) d'un matériau semiconducteur, adaptée pour former le canal du transistor, agencée en contact direct avec la couche ferroélectrique (2), ledit transistor NC-FET comportant en outre un canal (3b) agencé dans la couche active (3a), une source (11) et un drain (12) agencés dans la couche active (3a) de part et d'autre du canal (3b), et une grille (10) agencée sur le canal (3b), isolée dudit canal (3b) par un diélectrique de grille (30).