Invention Application
WO2005086791A3 HIGHLY PARALLEL SWITCHING SYSTEMS UTILIZING ERROR CORRECTION II
审中-公开
使用错误校正的高并行切换系统II
- Patent Title: HIGHLY PARALLEL SWITCHING SYSTEMS UTILIZING ERROR CORRECTION II
- Patent Title (中): 使用错误校正的高并行切换系统II
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Application No.: PCT/US2005007488Application Date: 2005-03-08
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Publication No.: WO2005086791A3Publication Date: 2006-10-05
- Inventor: REED COKE , MURPHY DAVID
- Applicant: INTERACTIC HOLDINGS LLC , REED COKE , MURPHY DAVID
- Assignee: INTERACTIC HOLDINGS LLC,REED COKE,MURPHY DAVID
- Current Assignee: INTERACTIC HOLDINGS LLC,REED COKE,MURPHY DAVID
- Priority: US55111004 2004-03-08; US56123104 2004-04-09
- Main IPC: H04Q11/00
- IPC: H04Q11/00 ; H04L12/56 ; H04Q3/68
Abstract:
An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and second stage networks each have more outputs than inputs. The data is first sent from the first device to the first stage network and then from the first stage network to the second stage network. The data is sent to the second device from the second stage network. The number of inputs to a device w the collection of devices from the second stage network exceeds the number of outputs from device w into the first stage network. The device w with N p input ports is capable of simultaneously receiving data from N p devices in the collection of devices. The latency through the entire system may be a fixed constant.
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