公开(公告)号：WO2007035437A3

公开(公告)日：2007-06-28

申请号：PCT/US2006035914

申请日：2006-09-15

Applicant: INTERACTIC HOLDINGS LLC ,  REED COKE ,  MURPHY DAVID

Inventor： REED COKE ,  MURPHY DAVID

IPC: H04L12/50

CPC classification number: H04L49/30 ,  H04L49/101 ,  H04L49/109 ,  H04L49/252

Abstract: An interconnect structure is disclosed comprising a collection of input ports, a collection of output ports, and a switching element. Data enters the switching element only at specific data entry times. The interconnect structure includes a collection of synchronizing elements. Data in the form of packets enter the input ports in an asynchronous fashion. The data packets pass from the input ports to the synchronizing units. The data exits the synchronizing units and enters the switching element with each packet arriving at the switching element at a specific data entry time.

Abstract translation: 公开了一种互连结构，其包括输入端口的集合，输出端口的集合以及开关元件。 数据仅在特定数据输入时间才进入开关元件。 互连结构包括同步元件的集合。 数据包的形式以异步方式输入输入端口。 数据包从输入端口传递到同步单元。 数据离开同步单元并且在特定数据输入时间的每个分组到达交换单元的情况下进入开关元件。

公开(公告)号：WO2005086791A3

公开(公告)日：2006-10-05

申请号：PCT/US2005007488

申请日：2005-03-08

Applicant: INTERACTIC HOLDINGS LLC ,  REED COKE ,  MURPHY DAVID

Inventor： REED COKE ,  MURPHY DAVID

IPC: H04Q11/00 ,  H04L12/56 ,  H04Q3/68

CPC classification number: H04Q3/68 ,  H04L12/18 ,  H04L49/101 ,  H04L49/15 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/254 ,  H04L49/3027 ,  H04L49/45 ,  H04L49/557 ,  H04L49/602

Abstract: An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and second stage networks each have more outputs than inputs. The data is first sent from the first device to the first stage network and then from the first stage network to the second stage network. The data is sent to the second device from the second stage network. The number of inputs to a device w the collection of devices from the second stage network exceeds the number of outputs from device w into the first stage network. The device w with N p input ports is capable of simultaneously receiving data from N p devices in the collection of devices. The latency through the entire system may be a fixed constant.

Abstract translation: 互连网络具有第一级网络和第二级网络以及网络外部的设备集合，使得第一设备能够向第二设备发送数据。 第一级网络连接到第二级网络的输入。 第一和第二级网络每个都具有比输入更多的输出。 数据首先从第一设备发送到第一级网络，然后从第一级网络发送到第二级网络。 数据从第二级网络发送到第二设备。 来自第二级网络的设备的收集的设备的输入数量超过从设备w进入第一级网络的输出的数量。 具有N个输入端口的设备w能够在设备集合中同时从N＆lt; p＆gt;设备接收数据。 整个系统的延迟可能是固定的常数。

公开(公告)号：WO2016057783A1

公开(公告)日：2016-04-14

申请号：PCT/US2015/054673

申请日：2015-10-08

Applicant: INTERACTIC HOLDINGS, LLC

Inventor： REED, Coke S. ,  DENNY, Ronald R. ,  IVES, Michael R. ,  DONNELLY, Terence J.

IPC: G06F17/14 ,  H04L12/861

CPC classification number: H04L67/10 ,  G06F17/14 ,  G06F17/142 ,  H04L41/04

Abstract: Techniques are disclosed relating to performing Fast Fourier Transforms (FFTs) using distributed processing. In some embodiments, results of local transforms that are performed in parallel by networked processing nodes are scattered across processing nodes in the network and then aggregated. This may transpose the local transforms and store data in the correct placement for performing further local transforms to generate a final FFT result. The disclosed techniques may allow latency of the scattering and aggregating to be hidden behind processing time, in various embodiments, which may greatly reduce the time taken to perform FFT operations on large input data sets.

Abstract translation: 公开了使用分布式处理执行快速傅里叶变换（FFT）的技术。 在一些实施例中，由网络处理节点并行执行的局部变换的结果分散在网络中的处理节点上，然后被聚合。 这可以转置局部变换并将数据存储在正确的位置，以进行进一步的局部变换以产生最终的FFT结果。 所公开的技术可以允许散射和聚合的等待时间在各种实施例中被隐藏在处理时间之后，这可以大大减少对大输入数据集执行FFT操作所花费的时间。

公开(公告)号：WO2016054264A1

公开(公告)日：2016-04-07

申请号：PCT/US2015/053321

申请日：2015-09-30

Applicant: INTERACTIC HOLDINGS, LLC

Inventor： REED, Coke S. ,  DENNY, Ronald R. ,  ROCKSTROH, Jay W. ,  IVES, Michael R.

IPC: G06F17/16 ,  H04L12/861

CPC classification number: H04L67/1097 ,  G06F17/16 ,  H04L47/70 ,  H04L49/90 ,  H04L67/2842

Abstract: Techniques are disclosed relating to parallel computing. In some embodiments, fine-grained data communication facilitates operations on large data sets such as multiplication of a sparse matrix by a vector. In this example, a first data set (the matrix) and a second data set (the vector) are distributed across multiple processing nodes. Performance of the overall multiplication operation may require communication of data among the processing nodes. In various embodiments, fine-grained communication of this data may reduce processing times and/or power consumption by avoiding congestion.

Abstract translation: 公开了关于并行计算的技术。 在一些实施例中，细粒度数据通信有助于对大数据集的操作，例如通过向量乘以稀疏矩阵。 在该示例中，第一数据集（矩阵）和第二数据集（矢量）分布在多个处理节点上。 整个乘法运算的性能可能需要在处理节点之间进行数据通信。 在各种实施例中，该数据的细粒度通信可以通过避免拥塞来减少处理时间和/或功耗。

公开(公告)号：WO2007035437A2

公开(公告)日：2007-03-29

申请号：PCT/US2006/035914

申请日：2006-09-15

Applicant: INTERACTIC HOLDINGS LLC ,  REED, Coke ,  MURPHY, David

Inventor： REED, Coke ,  MURPHY, David

IPC: H04L12/50

CPC classification number: H04L49/30 ,  H04L49/101 ,  H04L49/109 ,  H04L49/252

Abstract: An interconnect structure is disclosed comprising a collection of input ports, a collection of output ports, and a switching element. Data enters the switching element only at specific data entry times. The interconnect structure includes a collection of synchronizing elements. Data in the form of packets enter the input ports in an asynchronous fashion. The data packets pass from the input ports to the synchronizing units. The data exits the synchronizing units and enters the switching element with each packet arriving at the switching element at a specific data entry time.

Abstract translation: 公开了一种互连结构，其包括输入端口集合，输出端口集合和开关元件。 数据仅在特定的数据输入时间进入交换元件。 互连结构包括一组同步元件。 数据包形式的数据以异步方式进入输入端口。 数据包从输入端口传递到同步单元。 数据从同步单元退出并进入交换单元，每个数据包在特定的数据输入时间到达交换单元。

公开(公告)号：WO2003013061A1

公开(公告)日：2003-02-13

申请号：PCT/US2002/023411

申请日：2002-07-22

Applicant: INTERACTIC HOLDINGS, LLC ,  REED, Coke ,  HESSE, John

Inventor： REED, Coke ,  HESSE, John

IPC: H04L12/18

CPC classification number: H04L49/254 ,  H04L47/12

Abstract: This invention is directed to a parallel information generation, distribution and processing system (900). This scalable, pipelined control and switching system (900) efficiently and fairly manages a plurality of incoming data streams (132, 134), and applies class and quality of service requirements. The present invention also uses scalable MLML switch fabrics to control a data packet switch (930), including a request-processing switch (104) used to control the data-packet switch (930). Also included is a request processor (106) for each output port, which manages and approves all data flow to that output port, and an answer switch (108) which transmits answer packets from request processors (106) back to requesting input ports.

Abstract translation: 本发明涉及并行信息生成，分发和处理系统（900）。 这种可扩展的，流水线的控制和交换系统（900）有效和公平地管理多个输入数据流（132,134），并且应用类和服务质量要求。 本发明还使用可扩展的MLML交换结构来控制数据分组交换（930），包括用于控制数据分组交换（930）的请求处理交换机（104）。 还包括用于管理和批准到该输出端口的所有数据流的每个输出端口的请求处理器（106）和将请求处理器（106）的应答分组发送回请求输入端口的应答开关（108）。

公开(公告)号：WO2006069197A3

公开(公告)日：2007-06-07

申请号：PCT/US2005046482

申请日：2005-12-20

Applicant: INTERACTIC HOLDINGS LLC ,  REED COKE S ,  MURPHY DAVID

Inventor： REED COKE S ,  MURPHY DAVID

IPC: H04L12/56

CPC classification number: H04L49/45 ,  H04L49/15 ,  H04L49/201 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/357

Abstract: An interconnect structure comprises a plurality of network-connected devices and a logic (130) adapted to control a first subset os the network-connected devices (120) to transmit data and simultaneously control a second subset of the network-connected devices (140) to prepare for data transmission at a future time. The logic can execute an operation that actives a data transmission action upon realization of at least one predetermined criterion.

Abstract translation: 互连结构包括多个网络连接设备和适于控制网络连接设备（120）传输数据并同时控制网络连接设备（140）的第二子集的第一子系统的逻辑（130） 为将来的时间准备数据传输。 逻辑可以执行在实现至少一个预定标准时激活数据传输动作的操作。

公开(公告)号：WO2005124577A2

公开(公告)日：2005-12-29

申请号：PCT/US2005020701

申请日：2005-06-09

Applicant: INTERACTIC HOLDINGS LLC ,  REED COKE S ,  MURPHY DAVID

Inventor： REED COKE S ,  MURPHY DAVID

IPC: G06F15/173 ,  H04L12/28 ,  H04L12/56 ,  H04L29/08

CPC classification number: H04L45/00 ,  H04L45/742 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/201 ,  H04L49/3009 ,  H04L67/12

Abstract: In a system, a memory controller separates a memory into multiple banks and enables a plurality of selected banks to be accessed concurrently. The memory controller further comprises a logic that creates a representation of a tree structure in memory and builds routing tables accessed by pointers at nodes in the tree memory structure, and a logic that finds a target memory address based on a received Internet Protocol (IP) address used by the tree memory structure and the routing table.

Abstract translation: 在系统中，存储器控制器将存储器分离成多个存储体并且使多个所选择的存储体能够同时访问。 存储器控制器还包括在存储器中创建树结构的表示并构建通过树存储器结构中的节点处的指针访问的路由表的逻辑，以及基于接收到的因特网协议（IP）查找目标存储器地址的逻辑， 树存储器结构和路由表使用的地址。

公开(公告)号：WO2004045172A1

公开(公告)日：2004-05-27

申请号：PCT/US2003/034894

申请日：2003-11-05

Applicant: INTERACTIC HOLDINGS, LLC

Inventor： REED, Coke ,  MURPHY, David

IPC: H04L12/58

CPC classification number: H04L49/3072 ,  H04L49/1523 ,  H04L49/205 ,  H04L49/3018

Abstract: An interconnect structure (100) having a plurality of input ports and a plurality of output ports, including an input controller (150) which requests permission from predetermined logic within the structure to inject an entire message through two stages of data switches. The request contains only a portion of the address for a message target output with the amount of target output addresses supplied by the input controller (150) depending upon the data rate of the target output port.

Abstract translation: 具有多个输入端口和多个输出端口的互连结构（100），包括输入控制器（150），该输入控制器请求结构内的预定逻辑的许可以通过两级数据交换来注入整个消息。 该请求仅包含根据目标输出端口的数据速率的由输入控制器（150）提供的目标输出地址量的消息目标输出的地址的一部分。

公开(公告)号：WO0233899A3

公开(公告)日：2004-01-08

申请号：PCT/US0150542

申请日：2001-10-19

Applicant: INTERACTIC HOLDINGS LLC

Inventor： REED COKE S ,  HESS JOHN E

IPC: H04L12/56 ,  H04Q11/04 ,  G06F15/173

CPC classification number: H04L49/1553 ,  H04L2012/5651 ,  H04Q11/0478

Abstract: An interconnect structure and method of communicating messages on the interconnect structure assists high priority messages to travel through the interconnect structure at a faster rate than normal or low priority messages. An interconnect structure includes a plurality of nodes with a plurality of interconnect lines selectively coupling the nodes in a hierarchical multiple-level structure. Data moves from an uppermost source level to a lowermost destination level. Nodes in the structure are arranged in columns and levels. Nodes in the structure are arranged in columns and levels. Data wormholes through the structure and, in a given time-step, data always moves from onee column to an adjacent column and while remaining on the same level or moving down to a lower level. When data moves down a level, an additional bit of the target output is fixed so data exiting from the bottom of the structure arrives at the proper target output port.

Abstract translation: 在互连结构上传送消息的互连结构和方法有助于高优先级消息以比正常或低优先级消息更快的速率穿过互连结构。 互连结构包括具有多个互连线的多个节点，所述多个互连线以分级多级结构选择性地耦合节点。 数据从最上层源移动到最下层目的地。 结构中的节点以列和级别排列。 结构中的节点以列和级别排列。 通过结构的数据蠕虫洞，并且在给定的时间步长中，数据总是从一列移动到相邻的列，并且保持在相同的水平或向下移动到较低的水平。 当数据向下移动一个电平时，目标输出的附加位是固定的，所以从结构底部退出的数据到达正确的目标输出端口。