Invention Application
WO2006072094A8 APPARATUS AND METHOD FOR IMPROVING DRIVE STRENGTH, LEAKAGE AND STABILITY OF DEEP SUBMICRON MOS TRANSISTORS AND MEMORY CELLS 审中-公开
用于提高深层次级MOS晶体管和存储单元的驱动强度,泄漏和稳定性的装置和方法

  • Patent Title: APPARATUS AND METHOD FOR IMPROVING DRIVE STRENGTH, LEAKAGE AND STABILITY OF DEEP SUBMICRON MOS TRANSISTORS AND MEMORY CELLS
  • Patent Title (中): 用于提高深层次级MOS晶体管和存储单元的驱动强度,泄漏和稳定性的装置和方法
  • Application No.: PCT/US2005047671
    Application Date: 2005-12-28
  • Publication No.: WO2006072094A8
    Publication Date: 2007-04-26
  • Inventor: KAPOOR ASHOKSTRAIN ROBERTMARKO REUVEN
  • Applicant: SEMI SOLUTIONS LLC
  • Assignee: SEMI SOLUTIONS LLC
  • Current Assignee: SEMI SOLUTIONS LLC
  • Priority: US2718104 2004-12-29; US2954205 2005-01-04; US11045705 2005-04-19; US71776905 2005-09-19
  • Main IPC: H01L29/76
  • IPC: H01L29/76
APPARATUS AND METHOD FOR IMPROVING DRIVE STRENGTH, LEAKAGE AND STABILITY OF DEEP SUBMICRON MOS TRANSISTORS AND MEMORY CELLS
Abstract:
An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to existing MOS technology processes. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The invention is further useful for SRAM, DRAM, NVM devices and other memory cells.
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