公开(公告)号：WO2014062586A1

公开(公告)日：2014-04-24

申请号：PCT/US2013/064885

申请日：2013-10-14

Applicant: SEMI SOLUTIONS LLC ,  GOLD STANDARD SIMULATIONS LTD.

Inventor： KAPOOR, Ashok K. ,  STRAIN, Robert J.

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7853

Abstract: An improved fin field-effect transistor (FinFET) is built on a compound fin, which has a doped core and lightly doped epitaxial channel region between that core and the gate dielectric. The improved structure reduces FinFET random doping fluctuations when doping is used to control threshold voltage. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Three representative embodiments of the key structure are described in detail.

Abstract translation: 改进的鳍状场效应晶体管（FinFET）构建在复合鳍片上，复合鳍片在该芯体和栅极电介质之间具有掺杂的核心和轻掺杂的外延沟道区域。 当掺杂用于控制阈值电压时，改进的结构减少了FinFET随机掺杂波动。 此外，与现有技术的FinFET相比，晶体管设计提供更好的源极和漏极电导。 详细描述键结构的三个代表性实施例。

公开(公告)号：WO2006072094A3

公开(公告)日：2006-07-06

申请号：PCT/US2005/047671

申请日：2005-12-28

Applicant: SEMI SOLUTIONS LLC.

Inventor： KAPOOR, Ashok ,  STRAIN, Robert ,  MARKO, Reuven

IPC: H01L29/76

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to existing MOS technology processes. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The invention is further useful for SRAM, DRAM, NVM devices and other memory cells.

公开(公告)号：WO2006072094A8

公开(公告)日：2007-04-26

申请号：PCT/US2005047671

申请日：2005-12-28

Applicant: SEMI SOLUTIONS LLC

Inventor： KAPOOR ASHOK ,  STRAIN ROBERT ,  MARKO REUVEN

IPC: H01L29/76

CPC classification number: G11C11/412 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/404 ,  G11C16/0408 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/783

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to existing MOS technology processes. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The invention is further useful for SRAM, DRAM, NVM devices and other memory cells.

Abstract translation: 一种在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管的装置和方法，其中MOS晶体管具有区域效率，并且其中MOS晶体管的驱动强度和漏电流得到改善。 本发明使用不需要改变现有MOS技术过程的动态阈值电压控制方案。 本发明提供一种控制晶体管的阈值电压的技术。 在OFF状态下，将晶体管的阈值电压设定为高，将晶体管的漏电保持在较小的值。 在ON状态下，阈值电压设定为低值，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 本发明对于SRAM，DRAM，NVM器件和其他存储器单元更有用。

公开(公告)号：WO2006072094A2

公开(公告)日：2006-07-06

申请号：PCT/US2005047671

申请日：2005-12-28

Applicant: SEMI SOLUTIONS LLC

Inventor： KAPOOR ASHOK ,  STRAIN ROBERT ,  MARKO REUVEN

IPC: H01L29/76

CPC classification number: G11C11/412 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/404 ,  G11C16/0408 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/783

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to existing MOS technology processes. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The invention is further useful for SRAM, DRAM, NVM devices and other memory cells.

Abstract translation: 一种在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管的装置和方法，其中MOS晶体管是面积有效的，并且其中MOS晶体管的驱动强度和漏电流得到改善。 本发明使用不需要改变现有MOS技术过程的动态阈值电压控制方案。 本发明提供一种控制晶体管的阈值电压的技术。 在OFF状态下，将晶体管的阈值电压设定为高，将晶体管漏电保持在较小值。 在ON状态下，阈值电压被设定为低值，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 本发明对于SRAM，DRAM，NVM器件和其它存储器单元更有用。