Invention Application
- Patent Title: INTEGRATED CIRCUIT FABRICATION
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Application No.: PCT/US2006/007333Application Date: 2006-02-27
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Publication No.: WO2006104634A3Publication Date: 2006-10-05
- Inventor: TRAN, Luan, C. , LEE, John , LIU, Zengtao , FREEMAN, Eric , NIELSEN, Russell
- Applicant: MICRON TECHNOLOGY, INC. , TRAN, Luan, C. , LEE, John , LIU, Zengtao , FREEMAN, Eric , NIELSEN, Russell
- Applicant Address: 8000 South Federal Way, P.O. Box 6, Boise, Idaho 83707-0006 US
- Assignee: MICRON TECHNOLOGY, INC.,TRAN, Luan, C.,LEE, John,LIU, Zengtao,FREEMAN, Eric,NIELSEN, Russell
- Current Assignee: MICRON TECHNOLOGY, INC.,TRAN, Luan, C.,LEE, John,LIU, Zengtao,FREEMAN, Eric,NIELSEN, Russell
- Current Assignee Address: 8000 South Federal Way, P.O. Box 6, Boise, Idaho 83707-0006 US
- Agency: MALLON, Joseph
- Priority: US60/666,031 20050328; US11/216,477 20050831
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/033
Abstract:
A method for defining patterns in an integrated circuit (100) comprises defining a plurality of features in a first photoresist layer using photolithography over a first region (102) of a substrate (108). The method further comprises using pitch multiplication to produce at least two features (120) in a lower masking layer (116) for each feature in the photoresist layer. The features in the lower masking layer (116) include looped ends (124). The method further comprises covering with a second photoresist layer (126) a second region (104) of the substrate (108) including the looped ends (124) in the lower masking layer (116). The method further comprises etching a pattern of trenches in the substrate (108) through the features in the lower masking layer without etching in the second region (104). The trenches have a trench width.
Information query
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