公开(公告)号：WO2009079517A2

公开(公告)日：2009-06-25

申请号：PCT/US2008/087029

申请日：2008-12-16

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C.

Inventor： TRAN, Luan, C.

IPC: H01L21/336 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

Abstract translation: 半导体材料的连续环路的不同部分彼此电隔离。 在一些实施例中，环路的端部与环路的中间部分电隔离。 在一些实施例中，具有在其端部连接在一起的两个腿的半导体材料的环通过间距倍增过程形成，其中间隔物环形成在心轴的侧壁上。 去除心轴并且将一块掩模材料覆盖在间隔环的至少一端上。 在一些实施例中，掩模材料块覆盖间隔环的每一端。 由间隔物和块限定的图案被转移到半导体材料层。 这些块将所有环路电连接在一起。 沿循环的每条腿形成选择门。 这些块作为源/排水沟。 选择门被偏置在关闭状态以防止电流从环路的中部流向块，从而将中间部分与环的端部电隔离，并且还将环的不同的腿与每个 其他。

公开(公告)号：WO2005029570A1

公开(公告)日：2005-03-31

申请号：PCT/US2004/030367

申请日：2004-09-16

Applicant: MICRON TECHNOLOGY, INC ,  TRAN, Luan, C.

Inventor： TRAN, Luan, C.

IPC: H01L21/336

CPC classification number: H01L27/10876 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10891 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

Abstract: Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Poly-silicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

Abstract translation: 公开了自对准凹陷门结构和形成方法。 首先在半导体衬底中形成用于隔离的场氧化物区域。 多个列限定在形成在半导体衬底上的绝缘层中，接着在半导体衬底的暴露区域上形成薄的牺牲氧化物层，但不在场氧化物区域上。 然后在每列的侧壁和牺牲氧化物层和场氧化物区域的部分上方提供电介质材料。 进行第一蚀刻以在半导体衬底内形成第一组沟槽和在场氧化物区域内形成多个凹陷。 进行第二蚀刻以去除残留在柱的侧壁上的电介质残余物并形成第二组沟槽。 然后将多晶硅沉积在第二组沟槽内并在凹槽内形成凹陷的导电栅极。

公开(公告)号：WO2009079517A3

公开(公告)日：2009-10-01

申请号：PCT/US2008087029

申请日：2008-12-16

Applicant: MICRON TECHNOLOGY INC ,  TRAN LUAN C

Inventor： TRAN LUAN C

IPC: H01L21/336 ,  H01L21/027

CPC classification number: H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

Abstract translation: 连续的半导体材料环的不同部分彼此电隔离。 在一些实施例中，环路的末端与环路的中间部分电隔离。 在一些实施例中，具有在其端部连接在一起的两条腿的半导体材料的环由间距倍增工艺形成，其中间隔件的环形成在心轴的侧壁上。 去除心轴，并在间隔环的至少一端上覆盖一块掩模材料。 在一些实施例中，遮蔽材料块覆盖间隔环的每个端部。 由间隔物和块定义的图案被转移到半导体材料层。 这些模块将所有环路电连接在一起。 选择门沿着每个环的腿形成。 这些街区作为源头/渠道。 选择栅极偏置于关断状态以防止电流从环路的中间部分流向块，由此将中间部分与环路的端部电隔离并且还将环路的不同的支路与每个 其他。

公开(公告)号：WO2009017982A3

公开(公告)日：2009-04-02

申请号：PCT/US2008070407

申请日：2008-07-18

Applicant: MICRON TECHNOLOGY INC ,  TRAN LUAN C ,  GIRIDHAR RAGHUPATHY

Inventor： TRAN LUAN C ,  GIRIDHAR RAGHUPATHY

IPC: H01L21/027

CPC classification number: H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/1052

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

Abstract translation: 用于通过反向节距减小流动来制造器件的方法的实施例包括在衬底上形成特征的第一图案并且在形成第一图案的特征之后形成间距倍增间隔件的第二图案。 在本发明的实施例中，特征的第一图案可以通过光刻形成，并且间距倍增的间隔件的第二图案可以通过间距倍增形成。 提供了用于器件制造的其他方法。

公开(公告)号：WO2009018059A2

公开(公告)日：2009-02-05

申请号：PCT/US2008/070932

申请日：2008-07-23

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C.

Inventor： TRAN, Luan, C.

IPC: H01L21/027

CPC classification number: H01L21/0274 ,  H01L21/0337

Abstract: Spacers (175) are formed by pitch multiplication and a layer of negative photoresist (200) is deposited on and over the spacers (175) to form additional mask features. The deposited negative photoresist layer (200) is patterned, thereby removing photoresist from between the spacers (175) in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers (175) is facilitated. The pattern defined by the spacers (175) and the patterned negative photoresist is transferred to one or more underlying masking layers (130), (140) before being transferred to a substrate (110).

Abstract translation: 通过间距倍增形成间隔物（175），并且在间隔物（175）上和上方沉积负光致抗蚀剂（200）层以形成额外的掩模特征。 沉积的负光致抗蚀剂层（200）被图案化，由此在一些区域中从间隔物（175）之间去除光致抗蚀剂。 在图案化期间，不需要将光引导至需要去除负光刻胶的区域，并且促进从间隔物（175）之间清洁去除负光刻胶。 在被转移到衬底（110）之前，由间隔物（175）和图案化的负性光刻胶限定的图案被转移到一个或多个下面的掩模层（130），（140）。

公开(公告)号：WO2009018059A3

公开(公告)日：2009-04-02

申请号：PCT/US2008070932

申请日：2008-07-23

Applicant: MICRON TECHNOLOGY INC ,  TRAN LUAN C

Inventor： TRAN LUAN C

IPC: H01L21/027

CPC classification number: H01L21/0274 ,  H01L21/0337

Abstract: Spacers (175) are formed by pitch multiplication and a layer of negative photoresist (200) is deposited on and over the spacers (175) to form additional mask features. The deposited negative photoresist layer (200) is patterned, thereby removing photoresist from between the spacers (175) in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers (175) is facilitated. The pattern defined by the spacers (175) and the patterned negative photoresist is transferred to one or more underlying masking layers (130), (140) before being transferred to a substrate (110).

Abstract translation: 间隔物（175）由间距倍增形成，并且一层负性光致抗蚀剂（200）沉积在间隔物（175）上和上方以形成附加的掩模特征。 沉积的负性光致抗蚀剂层（200）被图案化，从而在一些区域中从间隔物（175）之间除去光致抗蚀剂。 在图案化期间，不需要将光引导到需要负光致抗蚀剂去除的区域，并且促进从间隔物（175）之间清洁去除负光致抗蚀剂。 由间隔物（175）和图案化的负性光致抗蚀剂限定的图案在被转移到基底（110）之前转移到一个或多个下面的掩蔽层（130），（140）。

公开(公告)号：WO2009020773A2

公开(公告)日：2009-02-12

申请号：PCT/US2008/071031

申请日：2008-07-24

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C.

Inventor： TRAN, Luan, C.

IPC: H01L21/302

CPC classification number: H01L21/76802 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L27/108 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Abstract translation: 制造包含与有源区特征对准的紧密间距接触并且使用各种技术来定义具有亚光刻尺寸的图案的同时制造自对准紧间距接触和导线的半导体结构的方法。 还公开了具有与有源区特征对齐的紧密间距触点的半导体结构以及任选地对准的导电线，半导体结构也具有紧密间距接触孔和用于导电线的对准沟槽。

公开(公告)号：WO2009017982A2

公开(公告)日：2009-02-05

申请号：PCT/US2008/070407

申请日：2008-07-18

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C. ,  GIRIDHAR, Raghupathy

Inventor： TRAN, Luan, C. ,  GIRIDHAR, Raghupathy

IPC: H01L21/027

CPC classification number: H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/1052

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

Abstract translation: 用于通过反向间距减小流程进行器件制造的方法的实施例包括在形成第一特征图案之后形成衬底上方的特征的第一图案并形成间距倍数间隔物的第二图案。 在本发明的实施例中，特征的第一图案可以通过光刻形成，并且间距倍增间隔物的第二图案可以通过间距倍增形成。 提供了其他用于器件制造的方法。

公开(公告)号：WO2009020773A3

公开(公告)日：2009-04-23

申请号：PCT/US2008071031

申请日：2008-07-24

Applicant: MICRON TECHNOLOGY INC ,  TRAN LUAN C

Inventor： TRAN LUAN C

IPC: H01L21/302

CPC classification number: H01L21/76802 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L27/108 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Abstract translation: 制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。 还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。

公开(公告)号：WO2007027558A3

公开(公告)日：2007-05-18

申请号：PCT/US2006033421

申请日：2006-08-28

Applicant: MICRON TECHNOLOGY INC ,  TRAN LUAN C

Inventor： TRAN LUAN C

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/8239

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/11521

Abstract: Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo- lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts (732), for example.

Abstract translation: 公开了形成用于集成电路的导电和/或半导电特征的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 这些特征可以在一个方向上具有减小的间距，在另一方向上可以具有较宽的间距。 常规的光刻步骤可以与俯仰减小技术组合使用以形成例如细长的俯仰特征，例如位线触点（732）。