Invention Application
- Patent Title: CHIP CAPACITIVE COUPLING
- Patent Title (中): 芯片电容耦合
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Application No.: PCT/US2006023366Application Date: 2006-06-14
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Publication No.: WO2006138494A3Publication Date: 2007-03-22
- Inventor: TREZZA JOHN
- Applicant: CUBIC WAFER INC , TREZZA JOHN
- Assignee: CUBIC WAFER INC,TREZZA JOHN
- Current Assignee: CUBIC WAFER INC,TREZZA JOHN
- Priority: US69075905 2005-06-14; US32995206 2006-01-10
- Main IPC: H01L29/40
- IPC: H01L29/40
Abstract:
A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.
Information query
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