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公开(公告)号:WO2023070372A1
公开(公告)日:2023-05-04
申请号:PCT/CN2021/126722
申请日:2021-10-27
Applicant: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
Inventor: ZHANG, Xin , SHENG, Jianjian , LV, Junyuan , LI, Zhenzhe
IPC: H01L29/40 , H01L29/20 , H01L29/778 , H01L21/335 , H01L27/06
Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a gate structure, a first field plate, and a second field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate structure is disposed above the second nitride-based semiconductor layer. The first field plate is disposed over the gate structure and is electrically coupled with the source electrode and the drain electrode. The second field plate is disposed over the gate structure and is electrically coupled with the gate structure. The first field plate and the second field plate are parallel with each other. A top surface of the first field plate faces a bottom surface of the second field plate to overlap with each other.
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公开(公告)号:WO2023043524A1
公开(公告)日:2023-03-23
申请号:PCT/US2022/036623
申请日:2022-07-11
Applicant: WOLFSPEED, INC.
Inventor: JONES, Evan , SRIRAM, Saptha , BOTHE, Kyle
IPC: H01L29/778 , H01L29/10 , H01L21/338 , H01L29/812 , H01L29/78 , H01L29/20 , H01L29/40 , H01L29/417
Abstract: A semiconductor device includes a substrate (322) having an upper surface (322A) including a recess region (360), a semiconductor structure (390) on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact (310), a drain contact (305), and a source contact (315) on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.
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公开(公告)号:WO2023021670A1
公开(公告)日:2023-02-23
申请号:PCT/JP2021/030464
申请日:2021-08-19
Applicant: オリンパス株式会社
Inventor: 小林 慧一
IPC: H01L27/146 , A61B1/05 , H01L21/28 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522 , H01L29/40 , H04N5/369
Abstract: 撮像ユニット1は、第1の主面10SAと第2の主面10SBとを有し、第1の主面10SAに受光回路11が形成され、第2の主面10SBに開口を有するビアホールH10の内面に貫通配線50が配設されている撮像基板10と、ビアホールH10の周囲の第2の主面10SBおよびビアホールH10の中の底面から第2の主面10SBに達しない範囲に配設されている半田レジスト膜60と、ビアホールH10の中に配設されている半田レジスト膜60の表面を覆っており、ビアホールH10の開口の外縁において、半田レジスト膜60に覆われていない貫通配線50と接合されている半田からなる接合端子70と、を有する。
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公开(公告)号:WO2023015494A1
公开(公告)日:2023-02-16
申请号:PCT/CN2021/112112
申请日:2021-08-11
Applicant: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
Inventor: HE, Chuan , PU, Xiaoqing , HAO, Ronghui , ZHANG, Jinhan , WONG, King Yuen
IPC: H01L29/40 , H01L29/778 , H01L21/335
Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers, a gate electrode, a first and a second field plates, and a first dielectric layer. The first field plate is disposed above the second nitride-based semiconductor layer. The second field plate is discontinuous and disposed above the second nitride-based semiconductor layer and in a position higher than the first field plate. The second field plate includes one or more enclosed discontinuities in a discontinuity region thereof. The first dielectric layer is disposed above the second field plate. The first dielectric layer covers and penetrates the second discontinuous field plate in the discontinuity region such that the second field plate encloses at least one portion of the first dielectric layer within its one or more enclosed discontinuities.
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公开(公告)号:WO2022262934A1
公开(公告)日:2022-12-22
申请号:PCT/EP2021/065943
申请日:2021-06-14
Inventor: KÜNNE, Matthias , SCHREIBER, Lars
IPC: H01L21/334 , H01L29/76 , H01L29/40 , H01L29/423 , H01L29/12 , H01L29/66 , B82Y10/00 , B82Y40/00 , H01L29/122 , H01L29/66977 , H01L29/7613
Abstract: Qubit-Element (1), umfassend eine Quantentopf-Struktur (2), innerhalb derer entlang einer ersten Richtung (x) ein Quantentopf (3) ausgebildet ist, eine Elektrodenanordnung (4), welche dazu eingerichtet ist, eine Bewegung eines Ladungsträgers in dem Quantentopf (3) in und entgegen einer zweiten Richtung (y) sowie in und entgegen einer dritten Richtung (z) einzuschränken, um einen Quantenpunkt (5) auszubilden, wobei die erste Richtung (x), die zweite Richtung (y) und die dritte Richtung (z) jeweils paarweise senkrecht zueinander stehen, eine aus verspanntem Silizium gebildete Grundschicht (6), welche entgegen der ersten Richtung (x) an die Quantentopf-Struktur (2) angrenzt.
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公开(公告)号:WO2022245886A1
公开(公告)日:2022-11-24
申请号:PCT/US2022/029736
申请日:2022-05-18
Applicant: WOLFSPEED, INC.
Inventor: BOTHE, Kyle , BISGES, Joshua
IPC: H01L29/40 , H01L23/00 , H01L29/417 , H01L29/423 , H01L21/338 , H01L29/778 , H01L23/31
Abstract: A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.
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公开(公告)号:WO2022245885A1
公开(公告)日:2022-11-24
申请号:PCT/US2022/029734
申请日:2022-05-18
Applicant: WOLFSPEED, INC.
Inventor: BISGES, Joshua , BOTHE, Kyle , KING, Matthew
IPC: H01L29/40 , H01L23/31 , H01L23/00 , H01L29/423 , H01L21/338 , H01L29/778 , H01L29/34 , H01L29/20 , H01L29/417
Abstract: A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.
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公开(公告)号:WO2022205081A1
公开(公告)日:2022-10-06
申请号:PCT/CN2021/084443
申请日:2021-03-31
Inventor: ZHU, Chunlin , LIU, Guoyou
IPC: H01L29/739 , H01L21/331 , H01L29/06 , H01L29/40
Abstract: There is provided a power semiconductor device 1, comprising: a semiconductor substrate 2 comprising: a base layer 5 selectively provided at a first side of the semiconductor substrate, and wherein the base layer has a first conductivity type; a collector layer 3 provided at a second side of the semiconductor substrate, wherein the second side is opposite to the first side, and wherein the collector layer has the first conductivity type; and a drift layer 4 having a second conductivity type opposite to the first conductivity type, wherein the drift layer is arranged between the collector layer 3 and the base layer 5; an active cell 15 provided in the semiconductor substrate 2, wherein the active cell 15 comprises an emitter region 7 which has the second conductivity type, an active base region 5-i which is a part of the base layer 5, an active gate trench 9 comprising a gate insulator 11 and an active gate electrode 10 disposed therein, and wherein the active gate trench 9 is configured to extend from a surface 16 of the semiconductor substrate 2 at the first side into the drift layer 4 along a first direction Y; and an insulation trench 17 provided in the substrate 2 and neighbouring the active cell 15, wherein the insulation trench 17 is filled with a dielectric material, wherein the active cell 15 has a first length L1 along a second direction X perpendicular to the first direction Y, and the insulation trench 17 has a second length L2 along the second direction X, and the first and second lengths L1 and L2 satisfy the relationship of 0.5 ≤ L2/L1 ≤ 2.
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公开(公告)号:WO2022194368A1
公开(公告)日:2022-09-22
申请号:PCT/EP2021/056856
申请日:2021-03-17
Applicant: HUAWEI TECHNOLOGIES CO., LTD. , MOUHOUBI, Samir
Inventor: MOUHOUBI, Samir
IPC: H01L29/778 , H01L29/423 , H01L29/40 , H01L29/10 , H01L29/45 , H01L29/47 , H01L29/20
Abstract: The present disclosure relates to a FET device (10), comprising a substrate (11), a GaN structure (15) covering a portion of the substrate (11), and a gate metal layer (17) on top of the GaN structure (15). The gate metal layer (17) comprises at least one first section (17-1) being formed from a first material composition, and a second section (17-2) being formed from a second material composition that is different from the first material composition, wherein a first interface (41) between the GaN structure (15) and the at least one first section (17-1) of the gate metal layer (17) has ohmic contact properties, and wherein a second interface (43) between the GaN structure (15) and the second section (17-2) of the gate metal layer (17) has non-ohmic contact properties
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公开(公告)号:WO2022178573A1
公开(公告)日:2022-09-01
申请号:PCT/AU2022/050131
申请日:2022-02-22
Applicant: MACQUARIE UNIVERSITY
Inventor: MAHON, Simon
IPC: H01L29/772 , H01L29/40 , H01L29/08 , H01L29/417 , H01L29/423 , H03K17/041 , H03K17/0812 , H03K17/687 , H03K17/16 , H04B1/403
Abstract: A semiconductor transistor device operable as a RF mixer is described. The device includes a field effect transistor with a field plate electrode. The field plate electrode is structured and located to be electromagnetically coupled to the gate electrode of the field effect transistor when carrying a radio frequency oscillation signal, to cause the field effect transistor to produce an output signal that is a mixed signal at the gate and the field plate. A semiconductor device for a radio receiver is also described. The device includes a field effect transistor with a field plate. A transient voltage signal is applied to the field plate responsive to detection of an interfering signal.
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